参数资料
型号: CS4362-KQZ
厂商: Cirrus Logic Inc
文件页数: 3/42页
文件大小: 0K
描述: IC DAC 6CH 114DB 192KHZ 48LQFP
标准包装: 250
位数: 24
数据接口: 串行
转换器数目: 6
电压电源: 模拟和数字
功率耗散(最大): 390mW
工作温度: -10°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 48-LQFP
供应商设备封装: 48-LQFP(7x7)
包装: 托盘
输出数目和类型: 6 电压,单极
采样率(每秒): 200k
产品目录页面: 757 (CN2011-ZH PDF)
其它名称: 598-1644
DS257F2
11
CS4362
SWITCHING CHARACTERISTICS - CONTROL PORT - IC FORMAT
(For KQZ TA = -10°C to +70°C; VLC = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLC, CL =30pF)
Notes:
19. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
20. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.
21.
for Single-Speed Mode,
for Double-Speed Mode,
for Quad-Speed Mode.
Parameter
Symbol
Min
Max
Unit
SCL Clock Frequency
fscl
-
100
kHz
RST Rising Edge to Start
tirs
500
-
ns
Bus Free Time Between Transmissions
tbuf
4.7
-
s
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
-
s
Clock Low time
tlow
4.7
-
s
Clock High Time
thigh
4.0
-
s
Setup Time for Repeated Start Condition
tsust
4.7
-
s
SDA Hold Time from SCL Falling
thdd
0-
s
SDA Setup time to SCL Rising
tsud
250
-
ns
Rise Time of SCL and SDA
trc, trc
-1
s
Fall Time SCL and SDA
tfc, tfc
-
300
ns
Setup Time for Stop Condition
tsusp
4.7
-
s
Acknowledge Delay from SCL Falling
tack
-
ns
15
256
Fs
×
---------------------
15
128
Fs
×
---------------------
15
64
Fs
×
------------------
t buf
t
hdst
t
lo w
t
hdd
t
high
t sud
Stop
S t a rt
SD A
SC L
t
irs
RS T
t
hdst
t
rc
t
fc
t sust
t susp
St a rt
Stop
R epe a t e d
t
rd
t
fd
t ack
Figure 3. Control Port Timing - IC Format
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