参数资料
| 型号： | CS4382A-CQZ |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 21/50页 |
| 文件大小： | 0K |
| 描述： | IC DAC 8CH 114DB 192KHZ 48LQFP |
| 标准包装： | 250 |
| 位数： | 24 |
| 数据接口： | 串行 |
| 转换器数目： | 8 |
| 电压电源： | 模拟和数字 |
| 功率耗散（最大）： | 680mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 托盘 |
| 输出数目和类型： | 16 电压，单极 |
| 采样率（每秒）： | 192k |
| 配用： | 598-1524-ND - BOARD EVAL FOR CS4382A DAC |
| 其它名称： | 598-1061 |
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28
DS618F2
CS4382A
Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute min-
imum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer
to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit.
4.12
Recommended Power-Up Sequence
4.12.1
Hardware Mode
1.
Hold RST low until the power supplies and configuration pins are stable, and the master and left/right
clocks are locked to the appropriate frequencies, as discussed in Section 4.1. In this state, the
registers are reset to the default settings, FILT+ will remain low, and VQ will be connected to VA/2.
If RST can not be held low long enough the SDINx pins should remain static low until all other clocks
are stable, and if possible the RST should be toggled low again once the system is stable.
2.
Bring RST high. The device will remain in a low power state with FILT+ low and will initiate the
Hardware power-up sequence after approximately 512 LRCK cycles in Single-Speed Mode (1024
LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode).
4.12.2
Software Mode
1.
Hold RST low until the power supply is stable, and the master and left/right clocks are locked to the
appropriate frequencies, as discussed in Section 4.1. In this state, the registers are reset to the default
settings; FILT+ will remain low, and VQ will be connected to VA/2.
2.
Bring RST high. The device will remain in a low-power state with FILT+ low for 512 LRCK cycles in
Single-speed Mode (1024 LRCK cycles in Double-speed Mode, and 2048 LRCK cycles in Quad-
speed Mode).
3.
In order to reduce the chances of clicks and pops, perform a write to the CP_EN bit prior to the
completion of approximately 512 LRCK cycles in Single-speed Mode (1024 LRCK cycles in Double-
speed Mode, and 2048 LRCK cycles in Quad-speed Mode). The desired register settings can be
loaded while keeping the PDN bit set to 1. Set the RMP_UP and RMP_DN bits to 1; then set the
format and mode control bits to the desired settings.
If more than the stated number of LRCK cycles passes before CPEN bit is written, the chip will enter
Hardware Mode and begin to operate with the M0-M3 as the mode settings. CPEN bit may be written
at anytime, even after the Hardware sequence has begun. It is advised that if the CPEN bit cannot be
set in time, the SDINx pins should remain static low (this way, no audio data can be converted
incorrectly by the Hardware Mode settings).
4.
Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 50 s.
Figure 17. Recommended Mute Circuitry
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CS4382A-CQZR | 功能描述:音频数/模转换器 IC IC 114dB 192 kHz 8Ch DAC w/DSD supt RoHS:否 制造商:Texas Instruments 转换器数量: 分辨率:16 bit 接口类型:I2S, UBS 转换速率: 信噪比:98 dB 工作电源电压:5 V DAC 输出端数量:2 工作温度范围:- 25 C to + 85 C 电源电流:23 mA 安装风格:SMD/SMT 封装 / 箱体:TQFP-32 封装:Reel |
| CS4382A-DQZ | 功能描述:音频数/模转换器 IC 8-Ch DAC 24-Bit 192kHz 114dB w/DSD RoHS:否 制造商:Texas Instruments 转换器数量: 分辨率:16 bit 接口类型:I2S, UBS 转换速率: 信噪比:98 dB 工作电源电压:5 V DAC 输出端数量:2 工作温度范围:- 25 C to + 85 C 电源电流:23 mA 安装风格:SMD/SMT 封装 / 箱体:TQFP-32 封装:Reel |
| CS4382A-DQZR | 功能描述:音频数/模转换器 IC IC 114dB 192 kHz 8Chn DAC w/DSD supt. RoHS:否 制造商:Texas Instruments 转换器数量: 分辨率:16 bit 接口类型:I2S, UBS 转换速率: 信噪比:98 dB 工作电源电压:5 V DAC 输出端数量:2 工作温度范围:- 25 C to + 85 C 电源电流:23 mA 安装风格:SMD/SMT 封装 / 箱体:TQFP-32 封装:Reel |
| CS4382A-EQZ | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:114 dB, 192 kHz 8-channel D/A Converter |
| CS4382A-EQZR | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:114 dB, 192 kHz 8-channel D/A Converter |
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