参数资料
型号: CS4382A-CQZ
厂商: Cirrus Logic Inc
文件页数: 27/50页
文件大小: 0K
描述: IC DAC 8CH 114DB 192KHZ 48LQFP
标准包装: 250
位数: 24
数据接口: 串行
转换器数目: 8
电压电源: 模拟和数字
功率耗散(最大): 680mW
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-LQFP
供应商设备封装: 48-LQFP(7x7)
包装: 托盘
输出数目和类型: 16 电压,单极
采样率(每秒): 192k
配用: 598-1524-ND - BOARD EVAL FOR CS4382A DAC
其它名称: 598-1061
DS618F2
33
CS4382A
6. REGISTER DESCRIPTION
Note:
All registers are read/write in IC Mode and write only in SPI, unless otherwise noted.
6.1
Mode Control 1 (Address 01h)
6.1.1
Control Port Enable (CPEN)
Default = 0
0 - Disabled
1 - Enabled
Function:
This bit defaults to 0, allowing the device to power-up in Stand-Alone Mode. The Control Port Mode can
be accessed by setting this bit to 1. This will allow the operation of the device to be controlled by the reg-
isters and the pin definitions will conform to Control Port Mode. To accomplish a clean power-up, the user
should write this bit within 10 ms following the release of Reset.
6.1.2
Freeze Controls (FREEZE)
Default = 0
0 - Disabled
1 - Enabled
Function:
This function allows modifications to be made to the registers without the changes taking effect until the
FREEZE is disabled. To make multiple changes in the Control Port registers take effect simultaneously,
enable the FREEZE Bit, make all register changes, then Disable the FREEZE bit.
6.1.3
Master Clock Divide Enable (MCLKDIV)
Default = 0
0 - Disabled
1 - Enabled
Function:
The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all other
internal circuitry.
6.1.4
DAC Pair Disable (DACx_DIS)
Default = 0
0 - DAC Pair x Enabled
1 - DAC Pair x Disabled
Function:
When the bit is set, the respective DAC channel pair (AOUTAx and AOUTBx) will remain in a reset state.
It is advised that changes to these bits be made while the power-down (PDN) bit is enabled to eliminate
the possibility of audible artifacts.
7
6
5
432
10
CPEN
FREEZE
MCLKDIV
DAC4_DIS
DAC3_DIS
DAC2_DIS
DAC1_DIS
PDN
0
000
01
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