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参数资料
| 型号： | CS48560-DQZR |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 13/23页 |
| 文件大小： | 0K |
| 描述： | IC DSP HP 32BIT 12CH I/O 48-QFP |
| 标准包装： | 2,000 |
| 系列： | CS485xx |
| 类型： | 定点 |
| 接口： | I²C，SPI |
| 时钟速率： | 150MHz |
| 芯片上RAM： | 96kB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.80V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 带卷 (TR) |
| 配用： | 598-1284-ND - KIT USB EVALUATION FOR CDB48500 |
5.10 Switching Characteristics—Serial Control Port–SPI Master Mode
5.10 Switching Characteristics—Serial Control Port–SPI Master Mode
Parameter
Symbol Min
Typical
Max
Units
SCP_CLK frequency 1
SCP_CS# falling to SCP_CLK rising 3
SCP_CLK low time
SCP_CLK high time
Setup time SCP_MISO input
Hold time SCP_MISO input
SCP_CLK low to SCP_MOSI output valid
SCP_CLK low to SCP_CS# falling
SCP_CLK low to SCP_CS# rising
Bus free time between active SCP_CS#
SCP_CLK falling to SCP_MOSI output high-Z
f spisck
t spicss
t spickl
t spickh
t spidsu
t spidh
t spidov
t spicsl
t spicsh
t spicsx
t spidz
—
—
20
20
13
5
—
7
—
—
—
—
11*DCLKP + (SCP_CLK PERIOD)/2
—
—
—
—
—
—
11*DCLKP + (SCP_CLK PERIOD)/2
3*DCLKP
—
F xtal /2 2
—
—
—
—
—
8
—
—
—
20
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.The specification f spisck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the
communication port may be limited by the firmware application.
3.SCP_CLK PERIOD refers to the period of SCP_CLK as being used in a given application. It does not refer to a tested parameter.
t spicsx
t spicss
EE_CS#
t spicsl
0
1
2
t spickl
6
7
0
5
6
7
t spicsh
SCP_CLK
f spisck
t spickh
SCP_MISO
A6
A5
A0
R/W
MSB
LSB
t spidsu
SCP_MOSI
t spidh
t spidov
MSB
LSB
t spidz
Figure 5-4. Serial Control Port–SPI Master Mode Timing
5.11 Switching Characteristics—Serial Control Port–I 2 C Slave Mode
Parameter
Symbol Min
Typical
Max
Units
SCP_CLK
frequency 1
f iicck
—
—
400
kHz
SCP_CLK low time
SCP_CLK high time
SCP_SCK rising to SCP_SDA rising or falling for START or STOP condition
START condition to SCP_CLK falling
SCP_CLK falling to STOP condition
Bus free time between STOP and START conditions
Setup time SCP_SDA input valid to SCP_CLK rising
Hold time SCP_SDA input after SCP_CLK falling
t iicckl
t iicckh
t iicckcmd
t iicstscl
t iicstp
t iicbft
t iicsu
t iich
1.25
1.25
1.25
1.25
2.5
3
100
20
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
μs
μs
μs
μs
μs
μs
ns
ns
13
DS734F5
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