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参数资料
| 型号： | CS48560-DQZR |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 14/23页 |
| 文件大小： | 0K |
| 描述： | IC DSP HP 32BIT 12CH I/O 48-QFP |
| 标准包装： | 2,000 |
| 系列： | CS485xx |
| 类型： | 定点 |
| 接口： | I²C，SPI |
| 时钟速率： | 150MHz |
| 芯片上RAM： | 96kB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.80V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 带卷 (TR) |
| 配用： | 598-1284-ND - KIT USB EVALUATION FOR CDB48500 |
5.12 Switching Characteristics—Serial Control Port–I2C Master Mode
Parameter
Symbol Min
Typical
Max
Units
SCP_CLK low to SCP_SDA out valid
SCP_CLK falling to SCP_IRQ# rising
NAK condition to SCP_IRQ# low
SCP_CLK rising to SCB_BSY# low
t iicdov
t iicirqh
t iicirql
t iicbsyl
—
—
—
—
—
—
3*DCLKP + 20
3*DCLKP + 20
18
3*DCLKP + 40
—
—
ns
ns
ns
ns
1.The specification f iicck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the
communication port may be limited by the firmware application. Flow control using the SCP_BSY# pin should be implemented to prevent overflow of
the input data buffer.
t iicckcmd
t iicckl
t iicr
t iicf
t iicckcmd
0
1
6
7
8
0
1
6
7
8
SCP_CLK
t iicstscl
t iicckh
t iicdov
f iicck
t iicstp
t iicbft
SCP_SDA
A6
A0
R/W
ACK
MSB
LSB
ACK
t iicirqh
t iicirql
t iicsu
t iich
SCP_IRQ#
t iiccbsyl
SCP_BSY#
Figure 5-5. Serial Control Port–I 2 C Slave Mode Timing
5.12 Switching Characteristics—Serial Control Port–I 2 C Master Mode
Parameter
Symbol
Min
Max
Units
SCP_CLK
frequency 1
f iicck
—
400
kHz
SCP_CLK low time
SCP_CLK high time
SCP_SCK rising to SCP_SDA rising or falling for START or STOP condition
START condition to SCP_CLK falling
SCP_CLK falling to STOP condition
Bus free time between STOP and START conditions
Setup time SCP_SDA input valid to SCP_CLK rising
Hold time SCP_SDA input after SCP_CLK falling
SCP_CLK low to SCP_SDA out valid
t iicckl
t iicckh
t iicckcmd
t iicstscl
t iicstp
t iicbft
t iicsu
t iich
t iicdov
1.25
1.25
1.25
1.25
2.5
3
100
20
—
—
—
—
—
—
—
—
—
18
μs
μs
μs
μs
μs
μs
ns
ns
ns
1.The specification f iicck indicates the maximum speed of the hardware. The system designer should be aware that the actual maximum speed of the
communication port may be limited by the firmware application.
14
DS734F5
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