参数资料
| 型号： | CS4955-CQZR |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 20/60页 |
| 文件大小： | 0K |
| 描述： | IC VID ENCODER NTSC/PAL 48-TQFP |
| 标准包装： | 2,000 |
| 类型： | 视频编码器 |
| 电压 - 电源，模拟： | 3.15 V ~ 5.25 V |
| 电压 - 电源，数字： | 3.15 V ~ 5.25 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-TQFP（7x7） |
| 包装： | 带卷 (TR) |
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CS4954 CS4955
DS278F6
27
5.13 VBI encoding
VBI (Vertical Blanking Interval) encoding is per-
formed according to SMPTE RP 188 recommenda-
tions. In NTSC mode, lines 10 - 20 and lines 272 -
283 are used for the transmission of ancillary data.
In PAL mode lines 6 - 22 and lines 318 -335 are
used. The VBI encoding mode can be set through
the CONTROL_3 register.
All digital input data is passed through the chip
when this mode is enabled. It is therefore the re-
sponsibility of the user to ensure appropriate ampli-
tude levels. Table 7 shows the relationship of the
digital input signal and the analog output voltage.
Each LSB corresponds to a step of 5 mV in the out-
put voltage.
5.14 Super White/Super Black support
The ITU-R BT.601 recommendation limits the al-
lowed range for the digital video data between
0×10 - 0×EB for luma and between 0×10 - 0×F0 for
the chrominance values. This chip will clip any
digital input value which is out of this range to con-
form to the ITU-R BT.601 specifications.
However for some applications it is useful to allow
a wider input range. By setting the CLIP_OFF bit
(CONTROL_6 register), the allowed input range is
extended to 0×01 - 0×FE for both luma and chromi-
nance values.
Note that 0×00 and 0×FF values are never allowed,
since they are reserved for synchronization infor-
mation.
5.15 Interrupts
In order to better support precise video mode
switches and to establish a software/hardware
handshake with the closed caption insertion block,
the CS4954/5 is equipped with an interrupt pin
named INT. The INT pin is active high. There are
three interrupt sources: VSYNC, Line 21, and Line
284. Each interrupt can be individually disabled
with the INT_EN Register. Each interrupt is also
cleared via writing a one to the corresponding
INT_CLR Register bits. The three individual inter-
rupts are OR-ed together to generate an interrupt
signal which is presented on the INT output pin. If
an interrupt has occurred, it cannot be eliminated
with a disable, it must be cleared.
5.16 General Purpose I/O Port
The CS4954/5 has a GPIO port and register that is
available when the device is configured for IC host
interface operation. In IC host interface mode, the
PDAT [7:0] pins are unused by the host interface
and they can operate as input or output pins for the
GPIO_DATA_REG
Register
(0×0A).
The
CS4954/5 also contains the GPIO_CTRL_REG
Register (0×09) which is used to configure the
GPIO pins for input or output operation.
The GPIO port PDAT [7:0] pins are configured for
input
operation
when
the
corresponding
GPIO_CTRL_REG [7:0] bits are set to 0. In GPIO
input mode, the CS4954/5 will latch the data on the
PDAT [7:0] pins into the corresponding bit loca-
Color
Cb
Cr
Y
White
0
+ 167
Yellow
- 84
+ 14
+ 156
Cyan
+ 28
- 84
+ 138
Green
- 56
- 70
+ 127
Magenta
+ 56
+ 70
+ 110
Red
- 28
+ 84
+ 99
Blue
+ 84
- 14
+ 81
Black
0
+ 70
Table 6. Internal Color Bar Values (8-bit values, Cb/Cr are in
twos complement format)
Digital Input
Analog Output Voltage
0
×38
286 mV
0
×3B
300 mV
0
×C4
1000 mV
Table 7. VBI Encoding Signal Amplitudes
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