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参数资料
| 型号： | CS497024-CVZR |
| 厂商： | CIRRUS LOGIC INC |
| 元件分类： | 消费家电 |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 封装： | LEAD FREE, LQFP-128 |
| 文件页数： | 18/19页 |
| 文件大小： | 454K |
| 代理商： | CS497024-CVZR |
CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
DS752PP10
8
4.2.7 Phase-locked Loop (PLL)-based Clock Generator
The low-jitter PLL generates integer or fractional multiples of a reference frequency which are used to clock the
DSP core and peripherals. Through a second PLL divider chain, a dependent clock domain can be output on
the DAO port for driving audio converters. The CS4970x4 defaults to running from the external reference
frequency and can be switched to use the PLL output after overlays have been loaded and configured, either
through master boot from an external FLASH or through host control. A built-in crystal oscillator circuit with a
buffered output is provided. The buffered output frequency ratio is selectable between 1:1 (default) or 2:1.
4.3 DSP I/O Description
4.3.1 Multiplexed Pins
Many of the CS4970x4 pins are multi-functional. For details on pin functionality please refer to the CS4970x4
System Designer’s Guide.
4.3.2 Termination Requirements
Open-drain pins on the CS4970x4 must be pulled high for proper operation. Please refer to the CS4970x4
System Designer’s Guide to identify which pins are open-drain and what value of pull-up resistor is required for
proper operation.
Mode select pins on the CS4970x4 are used to select the boot mode upon the rising edge of reset. A detailed
explanation of termination requirements for each communication mode select pin can be found in the
CS4970x4 System Designer’s Guide.
4.3.3 Pads
The CS4970x4 I/O operates from the 3.3 V supply and is tolerant within 5 V.
4.4 Application Code Security
The external program code may be encrypted by the programmer to protect any intellectual property it may
contain. A secret, customer-specific key is used to encrypt the program code that is to be stored external to the
device.
5 Characteristics and Specifications
Note:
All data sheet minimum and maximum timing parameters are guaranteed over the rated voltage
and temperature. All data sheet typical parameters are measured under the following conditions:
T=25 °C, CL = 20 pF, VDD = 1.8 V, VDDA = VDDIO = 3.3 V, GNDD = GNDIO = GNDA = 0 V.
5.1 Absolute Maximum Ratings
(GNDD = GNDIO = GNDA = 0 V; all voltages with respect to 0 V)
CAUTION: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is
not guaranteed at these extremes.
Parameter
Symbol
Min
Max
Unit
DC power supplies:
Core supply
PLL supply
I/O supply
|VDDA – VDDIO|
VDD
VDDA
VDDIO
–0.3
—
2.0
3.6
0.3
V
Input pin current, any pin except supplies
Iin
—+/- 10
mA
Input voltage on PLL_REF_RES
Vfilt
-0.3
3.6
V
Input voltage on I/O pins
Vinio
-0.3
5.0
V
Storage temperature
Tstg
-65
150
°C
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相关代理商/技术参数 |
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| CS497024-DVZ | 功能描述:IC DOLBY & DTS HD AUDIO DECODER 制造商:cirrus logic inc. 系列:CS4970xx 包装:* 零件状态:有效 类型:定点 接口:DAI/O，EBI/EMI，I2C，并联，SPI 时钟速率:25MHz 非易失性存储器:ROM（144kB） 片载 RAM:82kB 电压 - I/O:3.30V 电压 - 内核:1.80V 工作温度:-40°C ~ 85°C（TA） 安装类型:* 封装/外壳:* 供应商器件封装:* 标准包装:72 |
| CS497024-DVZR | 功能描述:IC DOLBY & DTS HD AUDIO DECODER 制造商:cirrus logic inc. 系列:CS4970xx 包装:* 零件状态:有效 类型:定点 接口:DAI/O，EBI/EMI，I2C，并联，SPI 时钟速率:25MHz 非易失性存储器:ROM（144kB） 片载 RAM:82kB 电压 - I/O:3.30V 电压 - 内核:1.80V 工作温度:-40°C ~ 85°C（TA） 安装类型:* 封装/外壳:* 供应商器件封装:* 标准包装:750 |
| CS4970X4 | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:32-bit High Definition Audio Decoder DSP Family |
| CS4970X4_09 | 制造商:CIRRUS 制造商全称:Cirrus Logic 功能描述:High Definition Audio Decoder DSP Family with Dual 32-bit DSP Engine Technology |
| CS4976-000 | 制造商:TE Connectivity 功能描述:44A1821-18-0/9-2-1KF/1 - Cable Rools/Shrink Tubing |
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