参数资料
型号: CS497024-CVZR
厂商: CIRRUS LOGIC INC
元件分类: 消费家电
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP128
封装: LEAD FREE, LQFP-128
文件页数: 4/19页
文件大小: 454K
代理商: CS497024-CVZR
CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
DS752PP10
12
5.9 Switching Characteristics — Internal Clock
5.10 Switching Characteristics — Serial Control Port - SPI Slave Mode
Parameter
Symbol
Min
Max
Unit
Internal DCLK frequency1
1. After initial power-on reset, Fdclk = Fxtal. After initial kick-start commands, the PLL is locked to max Fdclk and remains locked until
the next power-on reset.
Fdclk
—MHz
CS497004-CQZ
CS497004-CQZR
CS497024-CVZ
CS497024-CVZR
CS497014-CVZ
CS497014-CVZR
CS497024-CVZ
CS497024-CVZR
Fxtal
150
Internal DCLK period1
DCLKP
ns
CS497004-CQZ
CS497004-CQZR
CS497024-CVZ
CS497024-CVZR
CS497014-CVZ
CS497014-CVZR
CS497024-CVZ
CS497024-CVZR
6.7
1/Fxtal
Parameter
Symbol
Min
Typical
Max
Units
SCP_CLK frequency1
1. The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that the actual
maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_
BSY pin
should be implemented to prevent overflow of the input data buffer. At boot the maximum speed is Fxtal/3.
fspisck
——
25
MHz
SCP_CS falling to SCP_CLK rising
tspicss
24
ns
SCP_CLK low time
tspickl
20
ns
SCP_CLK high time
tspickh
20
ns
Setup time SCP_MOSI input
tspidsu
5—
ns
Hold time SCP_MOSI input
tspidh
5—
ns
SCP_CLK low to SCP_MISO output valid
tspidov
——
11
ns
SCP_CLK falling to SCP_IRQ rising
tspiirqh
20
ns
SCP_CS rising to SCP_IRQ falling
tspiirql
0—
ns
SCP_CLK low to SCP_CS rising
tspicsh
24
ns
SCP_CS rising to SCP_MISO output high-Z
tspicsdz
—20
ns
SCP_CLK rising to SCP_BSY falling
tspicbsyl
—3*DCLKP+20
ns
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