参数资料
| 型号： | CS5101EN14G |
| 厂商： | ON Semiconductor |
| 文件页数： | 4/9页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK 5V 1.5A 14DIP |
| 产品变化通告： | Product Obsolescence 07/Jul/2010 |
| 标准包装： | 25 |
| 类型： | 降压（降压） |
| 输出类型： | 固定 |
| 输出数： | 1 |
| 输出电压： | 5V |
| 输入电压： | 8 V ~ 45 V |
| 电流 - 输出： | 1.5A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 14-DIP（0.300"，7.62mm） |
| 包装： | 管件 |
| 供应商设备封装： | 14-PDIP |
CS5101
ELECTRICAL CHARACTERISTICS ( ? 40 ° C ≤ T A ≤ 85 ° C, ? 40 ° C ≤ T J ≤ 150 ° C, 10 V < V CC < 45 V, 8.0 V < V C < 75 V;
unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
Output Stage
V G , High
V G , Low
V G Rise Time
V G Fall Time
V G Resistance to GND
V D Resistance to GND
V SYNC = 5.0 V, IV G = 200 mA, V C ? V G
V SYNC = 0 V, IV G = 200 mA
Switch V SYNC High, C G = 1.0 nF, V CC = 15 V,
measure 2.0 V to 8.0 V
Switch V SYNC Low, C G = 1.0 nF, V CC = 15 V,
measure 8.0 V to 2.0 V
Remove supplies, V G = 10 V
Remove supplies, V D = 10 V
?
?
?
?
?
500
1.6
0.9
30
40
50
1500
2.5
1.5
75
100
100
?
V
V
ns
ns
k W
W
General
I CC , Operating
I CC in UVL
I CC in Sleep Mode High
I CC in Sleep Mode Low
I C , Operating High
I C , Operating Low
UVLO Start Voltage
UVLO Stop Voltage
UVLO Hysteresis
Leading Edge, t DELAY
Trailing Edge, t DELAY
V SYNC = 5.0 V
V CC = 6.0 V
V RAMP = 0 V, V CC = 45 V
V RAMP = 0 V, V CC = 10 V
V SYNC = 5.0 V, V FB = V IS ? = 0 V, V C = 75 V
V SYNC = 5.0 V, V FB = V IS ? = 0 V, V C = 8.0 V
?
?
?
V SYNC = 2.5 V to V G = 8.0 V
V SYNC = 2.5 V to V G = 2.0 V
?
?
?
?
?
?
7.4
6.4
0.8
?
?
12
300
80
20
4.0
3.0
8.0
7.0
1.0
280
750
18
500
200
50
8.0
6.0
9.2
8.3
1.2
?
?
mA
m A
m A
m A
mA
mA
V
V
V
ns
ns
PACKAGE PIN DESCRIPTION
PACKAGE LEAD #
PDIP ? 14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
?
?
SO ? 16WB
1
2
3
?
6
7
8
9
10
11
12, 13
14
15
16
5
4
LEAD SYMBOL
SYNC
V CC
V REF
LGND
V FB
COMP
RAMP
IS+
IS ?
IS COMP
PGND
V G
V C
V D
AGND
DGND
FUNCTION
Synchronization input.
Logic supply (10 V to 45 V).
5.0 V voltage reference.
Logic level ground (analog and digital ground tied).
Error amplifier inverting input.
Error amplifier output and compensation.
RAMP programmable with the external capacitor.
Current sense amplifier non ? inverting input.
Current sense amplifier inverting input.
Current sense amplifier compensation and output.
Power ground.
External power switch gate drive.
Output power stage supply voltage (8.0 V to 75 V).
External FET DRAIN voltage monitor.
Analog ground.
Digital ground.
http://onsemi.com
4
相关PDF资料 |
PDF描述 |
|---|---|
| CS51033GDR8G | IC REG CTRLR BUCK PWM 8-SOIC |
| CS51414GD8 | IC REG BUCK 1.5A 8SOIC |
| CS5157HGDR16G | IC CTRLR BUCK SYNC 5BIT 16-SOIC |
| CS5165AGDWR16G | IC CTRLR BUCK SYNC 5BIT 16-SOIC |
| CS5174GD8G | IC REG MULTI CONFIG 1.5A 8SOIC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CS5101-JL16 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Single-Ended Data Acquisition System |
| CS5101-JL8 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Single-Ended Data Acquisition System |
| CS5101-JP16 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Single-Ended Data Acquisition System |
| CS5101-JP8 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Single-Ended Data Acquisition System |
| CS5101-JU16 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Single-Ended Data Acquisition System |
发布紧急采购，3分钟左右您将得到回复。