参数资料
| 型号： | CS5101EN14G |
| 厂商： | ON Semiconductor |
| 文件页数： | 6/9页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK 5V 1.5A 14DIP |
| 产品变化通告： | Product Obsolescence 07/Jul/2010 |
| 标准包装： | 25 |
| 类型： | 降压（降压） |
| 输出类型： | 固定 |
| 输出数： | 1 |
| 输出电压： | 5V |
| 输入电压： | 8 V ~ 45 V |
| 电流 - 输出： | 1.5A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 14-DIP（0.300"，7.62mm） |
| 包装： | 管件 |
| 供应商设备封装： | 14-PDIP |
CS5101
Theory of Operation
The CS5101 is designed to regulate voltages in multiple
output power supplies. Functionally, it is similar to a
magnetic amplifier, operating as a switch with a delayed
turn ? on. It can be used with both single ended and dual
ended topologies.
The V FB voltage is monitored by the error amplifier EA.
It is compared to an internal reference voltage and the
amplified differential signal is fed through an inverting
amplifier into the buffer, BUF. The buffered signal is
compared at the PWM comparator with the ramp voltage
generated by capacitor C R . When the ramp voltage V R ,
exceeds the control voltage V C , the output of the PWM
comparator goes high, latching its state through the LATCH,
the output stage transistor Q 1 turns on, and the external
power switch, usually an N ? FET, turns on.
SYNC Function
The SYNC circuit is activated at time t 1 (Figure 3) when
the voltage at the SYNC pin exceeds the threshold level
(2.5V) of the SYNC comparator. The external ramp
capacitor C R is allowed to charge through the internal
current source I (200 m A). At time t 2 , the ramp voltage
intersects with the control voltage V C and the output of the
PWM comparator goes high, turning on the output stage and
the external power switch. At the same time, the PWM
comparator is latched by the RS latch, LATCH.
V SY V SY
1
0V
The logic state of the LATCH can be changed only when
both the voltage level of the trailing edge of the power pulse
at the SYNC pin is less than the threshold voltage of the
SYNC comparator (2.5 V) and the RAMP voltage is less than
the threshold voltage of the RAMP comparator (1.65 V). On
the negative going transition of the secondary side pulse
V SY , gate G 2 output goes high, resetting the latch at time t 3 .
Capacitor C R is discharged through transistor Q 4 . C R ’s
output goes low disabling the output stage, and the external
power switch (an N ? FET) is turned off.
RAMP Function
The value of the ramp capacitor C R is based on the
switching frequency of the regulator and the maximum duty
cycle of the secondary pulse V SY .
If the RAMP pin is pulled externally to 0.3 V or below, the
SSPR is disabled. Current drawn by the IC is reduced to less
than 100 m A, and the IC is in SLEEP mode.
FAULT Function
The voltage at the V CC pin is monitored by the
undervoltage lockout comparator with hysteresis. When
V CC falls below the UVL threshold, the 5.0 V reference and
all the circuitry running off of it is disabled. Under this
condition the supply current is reduced to less than 500 m A.
The V CC supply voltage is further monitored by the
V CC _OK comparator. When V CC is reduced below V REF
? 0.7 V, a fault signal is sent to gate G 1 . This fault signal,
which determines if V CC is absent, works in conjunction
with the ramp signal to disable the output, but only after the
current cycle has finished and the RS latch is reset.
Therefore this fault will not cause the output to turn off
during the middle of an on pulse, but rather will utilize
3
2
V SY + V D
0V
V SY
4
0V
V SY ? V OUT
V D
V C
V RAMP
V DS
V S
V L1
lossless turn ? off. This feature protects the FET from
overvoltage stress. This is accomplished through gate G 1 by
driving transistor Q 4 on.
An additional fault signal is derived from the REF_OK
comparator. V REF is monitored so to disable the output
through gate G 1 when the V REF voltage falls below the OK
threshold. As in the V CC _OK fault, the REF_OK fault
disables the output after the current cycle has been
completed. The fault logic will operate normally only when
V REF voltage is within the specification limits of REF_OK.
DRAIN Function
5
0V
V OUT + V D
The drain pin, V D monitors the voltage on the drain of the
power switch and derives energy from it to keep the output
V SY + V C
6
0V
Ground Level
(Gate doesn’t go
below GND)
t 1 t 2 t 3
t 4 t 1
V D
V G
stage in an off state when V C or V CC is below the minimum
specified voltage.
Figure 3. Waveforms for CS5101. The Number to
the Left of Each Curve Refers to a Node On the
Application Diagram on Page 2.
http://onsemi.com
6
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