参数资料
型号: CS51033GD8
厂商: ON Semiconductor
文件页数: 6/10页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM 8-SOIC
产品变化通告: Product Obsolescence 11/Feb/2009
Product Obsolescence 30/Dec/2003
标准包装: 98
PWM 型: 控制器
输出数: 1
频率 - 最大: 240kHz
占空比: 83.3%
电源电压: 3 V ~ 16 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
包装: 管件
CS51033
Buck Regulator Operation
A block diagram of a typical buck regulator is shown in
Figure 4. If we assume that the output transistor is initially
off, and the system is in discontinuous operation, the
inductor current I L is zero and the output voltage is at its
nominal value. The current drawn by the load is supplied by
the output capacitor C O . When the voltage across C O drops
below the threshold established by the feedback resistors R1
and R2 and the reference voltage V REF , the power transistor
Q1 switches on and current flows through the inductor to the
output. The inductor current rises at a rate determined by
(V IN ? V OUT )/Load. The duty cycle (or “on” time) for the
CS51033 is limited to 80%. If output voltage remains higher
than nominal during the entire C OSC change time, the Q1
does not turn on, skipping the pulse.
V IN
C IN
Q 1
L
R 1
D 1
C O
R LOAD
R 2
Control
Feedback
Figure 4. Buck Regulator Block Diagram
Charge Pump Circuit
(Refer to the CS51033 Application Diagram on page 2).
An external charge pump circuit is necessary when the V C
input voltage is below 5.0 V to ensure that there is suffifient
gate drive voltage for the external FET. When V IN is applied,
capacitors C1 and C2 will be charged to a diodes drop below
FET turns on, it’s drain voltage will be approximately equal
to V IN . Since the voltage across C1 can not change
instantaneously, D2 is reverse biased and the anode voltage
rises to approximately 2.0 × 3.3 V ? VD2. C1 transfers some
of its stored charge C2 via D3. After several cycles there is
sufficient gate drive voltage.
V IN via diodes D2 and D4, respectively. When the P?Ch
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