参数资料
型号: CS51033GD8
厂商: ON Semiconductor
文件页数: 7/10页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM 8-SOIC
产品变化通告: Product Obsolescence 11/Feb/2009
Product Obsolescence 30/Dec/2003
标准包装: 98
PWM 型: 控制器
输出数: 1
频率 - 最大: 240kHz
占空比: 83.3%
电源电压: 3 V ~ 16 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
包装: 管件
CS51033
APPLICATIONS INFORMATION
IMAX + OUT
+ 3.0 A ) 0.6 A 2.0 + 3.3 A
VOUT ) VD
VIN * VSAT
D + OUT
CO +
+
^ 11.4 m F
ESR + D V + 50 10 * 3 + 55 m W
COSC +
^ 470 pF
103
FSW
1 * *
FSW
VOUT + 1.25 V R1 ) R2 + 1.25 V R1 ) 1.0
LMIN +
VOUT ) VD TOFF(MAX) 2.1 V 4.3 m s
D I
+ ^ 15 m H
1.5 V + R1 ) R2 + 1.5 k W
* 1.0 + 1.0 k W 1.5 V + 200 W
R1 + R2
DESIGNING A POWER SUPPLY WITH THE CS51033
Specifications
? V IN = 3.3 V ± 10% (i.e. 3.63 V max., 2.97 V min.)
? V OUT = 1.5 V ± 2.0%
? I OUT = 0.3 A to 3.0 A
? Output ripple voltage < 33 mV.
? F SW = 200 kHz
1) Duty Cycle Estimates
Since the maximum duty cycle D, of the CS51033 is
limited to 80% min., it is best to estimate the duty cycle for
the various input conditions to see that the design will work
over the complete operating range.
The duty cycle for a buck regulator operating in a
continuous conduction mode is given by:
D +
where:
V SAT = R DS(ON) × I OUT Max.
In this case we can assume that V D = 0.6 V and V SAT =
0.6 V so the equation reduces to:
V
VIN
From this, the maximum duty cycle D MAX is 53%, this
occurs when V IN is at it’s minimum while the minimum duty
cycle D MIN is 0.35%.
2) Switching Frequency and On and Off Time
Calculations
F SW = 200 kHz. The switching frequency is determined
by C OSC , whose value is determined by:
95
2
30
3 106 FSW
T + 1.0 + 5.0 m s
FSW
TON(MAX) + 5.0 m s 0.53 + 2.65 m s
TON(MIN) + 5.0 m s 0.35 + 1.75 m s
TOFF(MAX) + 5.0 m s * 0.7 m s + 4.3 m s
3) Inductor Selection
Pick the inductor value to maintain continuous mode
operation down to 0.3 Amps.
The ripple current D I = 2 × I OUT(MIN) = 2 × 0.3 A = 0.6 A.
0.6 A
The CS51033 will operate with almost any value of
inductor. With larger inductors the ripple current is reduced
and the regulator will remain in a continuous conduction
mode for lower values of load current. A smaller inductor
will result in larger ripple current. The core must not saturate
with the maximum expected current, here given by:
I ) D I
2.0
4) Output Capacitor
The output capacitor limits the output ripple voltage. The
CS51033 needs a maximum of 15 mV of output ripple for
the feedback comparator to change state. If we assume that
all the inductor ripple current flows through the output
capacitor and that it is an ideal capacitor (i.e. zero ESR), the
minimum capacitance needed to limit the output ripple to
50 mV peak?to?peak is given by:
D I
8.0 FSW D V
0.6 A
8.0 (200 103 Hz) (33 10 * 3 V)
The minimum ESR needed to limit the output voltage
ripple to 50 mV peak?to?peak is:
D I 0.6 A
The output capacitor should be chosen so that its ESR is
at least half of the calculated value and the capacitance is at
least ten times the calculated value. It is often advisable to
use several capacitors in parallel to reduce ESR.
Low impedance aluminum electrolytic, tantalum or
organic semiconductor capacitors are a good choice for an
output capacitor. Low impedance aluminum are the
cheapest but are not available in surface mount at present.
Solid tantalum chip capacitors are available from a number
of suppliers and offer the best choice for surface mount
applications. The capacitor working voltage should be
greater than the output voltage in all cases.
5) V FB Divider
R2 R2
The input bias current to the comparator is 4.0 m A. The
resistor divider current should be considerably higher than
this to ensure that there is sufficient bias current. If we
choose the divider current to be at least 250 times the bias
current this gives a divider current of 1.0 mA and simplifies
the calculations.
1.0 mA
Let R2 = 1.0 k
Rearranging the divider equation gives:
VOUT
1.25 1.25
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