参数资料
| 型号： | CS5157HGDR16 |
| 厂商： | ON Semiconductor |
| 文件页数： | 3/16页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR BUCK SYNC 5BIT 16SOIC |
| 产品变化通告： | Product Obsolescence 23/Nov/2010 Product Obsolescence 30/Dec/2003 |
| 标准包装： | 2,500 |
| 应用： | 控制器，Intel Pentium? II |
| 输入电压： | 4.25 V ~ 20 V |
| 输出数： | 2 |
| 输出电压： | 1.3 V ~ 2.05 V，2.1 V ~ 3.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 带卷 (TR) |
| 其它名称： | CS5157HGDR16OS |
CS5157H
ELECTRICAL CHARACTERISTICS (0 ° C < T A < +70 ° C; 0 ° C < T J < +125 ° C; 8.0 V < V CC1 < 14 V; 5.0 V < V CC2 < 20 V;DAC Code:
V ID4 = V ID2 = V ID1 = V ID0 = 1; V ID3 = 0 ; CV GATE(L) and CV GATE(H) = 1.0 nF; C OFF = 330 pF; C SS = 0.1 m F, unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
Error Amplifier
V FB Bias Current
Open Loop Gain
Unity Gain Bandwidth
COMP SINK Current
COMP SOURCE Current
COMP CLAMP Current
COMP High Voltage
COMP Low Voltage
PSRR
V FB = 0 V
1.25 V < V COMP < 4.0 V; (Note 2)
(Note 2)
V COMP = 1.5 V; V FB = 3.0 V; V SS > 2.0 V
V COMP = 1.2 V; V FB = 2.7 V; V SS = 5.0 V
V COMP = 0 V; V FB = 2.7 V
V FB = 2.7 V; V SS = 5.0 V
V FB = 3.0 V
8.0 V < V CC1 < 14 V @ 1.0 kHz; (Note 2)
?
50
500
0.4
30
0.4
4.0
?
60
0.3
60
3000
2.5
50
1.0
4.3
160
85
1.0
?
?
8.0
80
1.6
5.0
600
?
m A
dB
kHz
mA
m A
mA
V
mV
dB
V CC1 Monitor
Start Threshold
Stop Threshold
Hysteresis
Output switching
Output not switching
Start?Stop
3.75
3.70
?
3.90
3.85
50
4.05
4.00
?
V
V
mV
V GATE(H) and V GATE(L)
Out SOURCE Sat at 100 mA
Out SINK Sat at 100 mA
Out Rise Time
Measure V CC1 ? V GATE(L) ; V CC2 ? V GATE(H)
Measure V GATE(H) ? V PGND ; V GATE(L) ? V PGND
1.0 V < V GATE(H) < 9.0 V; 1.0 V < V GATE(L) < 9.0 V;
?
?
?
1.2
1.0
30
2.0
1.5
50
V
V
ns
V CC1 = V CC2 = 12 V
Out Fall Time
9.0 V > V GATE(H) > 1.0 V; 9.0 V > V GATE(L) > 1.0 V;
?
30
50
ns
V CC1 = V CC2 = 12 V
Delay V GATE(H) to V GATE(L)
V GATE(H) falling to 2.0 V; V CC1 = V CC2 = 8.0 V;
?
25
50
ns
V GATE(L) rising to 2.0 V
Delay V GATE(L) to V GATE(H)
V GATE(L) falling to 2.0 V; V CC1 = V CC2 = 8.0 V;
?
25
50
ns
V GATE(H) rising to 2.0 V
V GATE(H) , V GATE(L) Resistance
V GATE(H) , V GATE(L) Schottky
Resistor to LGND (Note 2)
LGND to V GATE(H) @ 10 mA
20
?
50
600
100
800
k W
mV
LGND to V GATE(L) @ 10 mA
Soft?Start (SS)
Charge Time
Pulse Period
Duty Cycle
COMP Clamp Voltage
V FFB SS Fault Disable
High Threshold
?
?
(Charge Time /Pulse Period) × 100
V FB = 0 V; V SS = 0
V GATE(H) = Low; V GATE(L) = Low
?
1.6
25
1.0
0.50
0.9
?
3.3
100
3.3
0.95
1.0
2.5
5.0
200
6.0
1.10
1.1
3.0
ms
ms
%
V
V
V
PWM Comparator
Transient Response
V FFB = 0 to 5.0 V to V GATE(H) = 9.0 V to 1.0 V;
?
100
125
ns
V CC1 = V CC2 = 12 V
V FFB Bias Current
V FFB = 0 V
?
0.3
?
m A
2. Guaranteed by design, not 100% tested in production.
http://onsemi.com
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