参数资料
型号: CS5157HGDR16
厂商: ON Semiconductor
文件页数: 6/16页
文件大小: 0K
描述: IC CTRLR BUCK SYNC 5BIT 16SOIC
产品变化通告: Product Obsolescence 23/Nov/2010
Product Obsolescence 30/Dec/2003
标准包装: 2,500
应用: 控制器,Intel Pentium? II
输入电压: 4.25 V ~ 20 V
输出数: 2
输出电压: 1.3 V ~ 2.05 V,2.1 V ~ 3.5 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.154",3.90mm 宽)
供应商设备封装: 16-SOIC
包装: 带卷 (TR)
其它名称: CS5157HGDR16OS
CS5157H
V CC2
V CC1
V CC1 Monitor
? Comparator
+
5.0 V
SS Low
V GATE(H)
3.90 V
?
Comparator
R
Q
FAULT
3.85V
60 m A
+
S
Q
FAULT
PGnd
SS
2.0 m A
0.7 V
+
SS High
Comparator
FAULT
Latch
V CC1
V ID0
V ID1
V ID2
V ID3
5 BIT
DAC
Error
Amplifier
+
?
PWM
2.5 V
?
V GATE(L)
PGnd
V ID4
Comparator
?
V FB
Slow Feedback
+
Maximum
On?Time
Timeout
R
S
Q
Q
GATE(H) = ON
GATE(H) = OFF
COMP
Normal
Off?Time
Timeout
PMW
Latch
C OFF
One Shot
V FFB
Fast Feedback
?
+
Extended
Off?Time
Timeout
Off?Time
Timeout
R
S
Q
C OFF
LGnd
1.0 V
V FFB Low
Comparator
PWM COMP
Time?Out
Timer
(30 m s)
Edge Triggered
Figure 2. Block Diagram
APPLICATIONS INFORMATION
THEORY OF OPERATION
PWM
Comparator
V 2 Control Method
The V 2 method of control uses a ramp signal that is
+
?
C
V GATE(H)
V GATE(L)
generated by the ESR of the output capacitors. This ramp is
proportional to the AC current through the main inductor
and is offset by the value of the DC output voltage. This
control scheme inherently compensates for variation in
Ramp
Signal
V FFB
Output
either line or load conditions, since the ramp signal is
generated from the output voltage itself. This control
scheme inherently compensates for variation in either line or
load conditions, since the ramp signal is generated from the
output voltage itself. This control scheme differs from
traditional techniques such as voltage mode, which
COMP
Error
Signal
Error
Amplifier
E
?
+
Voltage
Feedback
V FB
Reference
Voltage
generates an artificial ramp, and current mode, which
generates a ramp from inductor current.
http://onsemi.com
6
Figure 3. V 2 Control Diagram
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