参数资料
| 型号： | CS5157HGDR16G |
| 厂商： | ON Semiconductor |
| 文件页数： | 5/16页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR BUCK SYNC 5BIT 16-SOIC |
| 产品变化通告： | Product Obsolescence 24/Jan/2011 |
| 标准包装： | 1 |
| 应用： | 控制器，Intel Pentium? II |
| 输入电压： | 4.25 V ~ 20 V |
| 输出数： | 2 |
| 输出电压： | 1.3 V ~ 2.05 V，2.1 V ~ 3.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 剪切带 (CT) |
| 其它名称： | CS5157HGDR16GOSCT |
CS5157H
ELECTRICAL CHARACTERISTICS (0 ° C < T A < +70 ° C; 0 ° C < T J < +125 ° C; 8.0 V < V CC1 < 14 V; 5.0 V < V CC2 < 20 V;DAC Code:
V ID4 = V ID2 = V ID1 = V ID0 = 1; V ID3 = 0 ; CV GATE(L) and CV GATE(H) = 1.0 nF; C OFF = 330 pF; C SS = 0.1 m F, unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
Supply Current
I CC1
I CC2
Operating I CC1
Operating I CC2
No Switching
No Switching
V FB = COMP = V FFB
V FB = COMP = V FFB
?
?
?
?
8.5
1.6
8.0
2.0
13.5
3.0
13
5.0
mA
mA
mA
mA
C OFF
Normal Charge Time
Extension Charge Time
Discharge Current
V FFB = 1.5 V; V SS = 5.0 V
V SS = V FFB = 0
C OFF to 5.0 V; V FB > 1.0 V
1.0
5.0
5.0
1.6
8.0
?
2.2
11.0
?
m s
m s
mA
Time Out Timer
Time Out Time
V FB = V COMP ; V FFB = 2.0 V;
10
30
65
m s
Record V GATE(H) Pulse High Duration
Fault Mode Duty Cycle
V FFB = 0V
35
50
70
%
PACKAGE PIN DESCRIPTION
PACKAGE PIN #
SOIC?16
1, 2, 3, 4, 6
5
7
8
9
10
11
12
13
14
15
16
PIN SYMBOL
V ID0 ?V ID4
SS
C OFF
V FFB
V CC2
V GATE(H)
PGND
V GATE(L)
V CC1
LGND
COMP
V FB
FUNCTION
Voltage ID DAC input pins. These pins are internally pulled up to 5.0 V providing logic ones if left
open. V ID4 selects the DAC range. When V ID4 is High (logic one), the DAC range is 2.10 V to
3.50 V with 100 mV increments. When V ID4 is Low (logic zero), the DAC range is 1.30 V to
2.05 V with 50 mV increments. V ID0 ? V ID4 select the desired DAC output voltage. Leaving all
5 DAC input pins open results in a DAC output voltage of 1.2440 V, allowing for adjustable output
voltage, using a traditional resistor divider.
Soft?Start Pin. A capacitor from this pin to LGND in conjunction with internal 60 m A current
source provides Soft?Start function for the controller. This pin disables fault detect function
during Soft?Start. When a fault is detected, the Soft?Start capacitor is slowly discharged by
internal 2.0 m A current source setting the time out before trying to restart the IC.
Charge/discharge current ratio of 30 sets the duty cycle for the IC when the regulator output is
shorted.
A capacitor from this pin to ground sets the time duration for the on board one shot, which is
used for the constant off time architecture.
Fast feedback connection to the PWM comparator. This pin is connected to the regulator output.
The inner feedback loop terminates on time.
Boosted power for the high side gate driver.
High FET driver pin capable of 1.5 A peak switching current. Internal circuit prevents V GATE(H)
and V GATE(L) from being in high state simultaneously.
High current ground for the IC. The MOSFET driver is referenced to this pin. Input capacitor
ground and the source of lower FET should be tied to this pin.
Low FET driver pin capable of 1.5 A peak switching current.
Input power for the IC and low side gate driver.
Signal ground for the IC. All control circuits are referenced to this pin.
Error amplifier compensation pin. A capacitor to ground should be provided externally to
compensate the amplifier.
Error amplifier DC feedback input. This is the master voltage feedback which sets the output
voltage. This pin can be connected directly to the output or a remote sense trace.
http://onsemi.com
5
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