- 您现在的位置：买卖IC网 > PDF目录15085 > CS5301GDWR32 (ON Semiconductor)IC REG CTRLR BUCK PWM 32-SOIC PDF资料下载
参数资料
| 型号： | CS5301GDWR32 |
| 厂商： | ON Semiconductor |
| 文件页数： | 16/19页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 32-SOIC |
| 标准包装： | 1 |
| PWM 型： | 电流/电压模式，V²? |
| 输出数： | 1 |
| 频率 - 最大： | 1MHz |
| 电源电压： | 4.7 V ~ 20 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 32-SOIC（0.295"，7.50mm 宽） |
| 包装： | 剪切带 (CT) |
| 其它名称： | CS5301GDWR32OSCT |
CS5301
works against 10 k W (R10) to limit the window of fast
slewing to 300 mV ? enough to allow for fast transients, but
not enough to interfere with soft?start. This window will be
noticeable as a step in the COMP pin voltage at startup. The
size of this step must be kept smaller than the Channel
Startup Offset (nominally 0.4 V) for proper soft?start
operation. If adaptive positioning is used the R9 and R8 form
a divider with the V DRP end held at the DAC voltage during
startup, which effectively makes the Channel Startup Offset
larger.
C12 is included for error amp stability. A capacitive load
is required on the error amp output. Use of values less than
1.0 nF may result in error amp oscillation of several MHz.
C11 and the parallel resistance of the V FB resistor (R9)
and the V DRP resistor (R8) are used to roll off the error amp
gain. The gain is rolled off at high enough frequency to give
a quick transient response, but low enough to cross zero dB
well below the switching frequency to minimize ripple and
noise on the COMP pin.
+12 V
+5.0 V
50 k
COMP
100 k
Voltage feedback should be taken from a point of the
output or the output filter that doesn’t favor any one phase.
If the feedback connection is closer to one inductor than the
others the ripple associated with that phase may appear
larger than the ripple associated with the other phases and
poor current sharing can result.
The current sense signal is typically tens of milli?volts.
Noise pick?up should be avoided wherever possible.
Current feedback traces should be routed away from noisy
areas such as switch nodes and gate drive signals. The paths
should be matched as well as possible. It is especially
important that all current sense signals be picked off at
similar points for accurate current sharing. If the current
signal is taken from a place other than directly at the inductor
any additional resistance between the pick?off point and the
inductor appears as part of the inherent inductor resistance
and should be considered in design calculations. Capacitors
for the current feedback networks should be placed as close
to the current sense pins as practical.
DESIGN PROCEDURE
Current Sensing, Power Stage and Output Filter
Components
1. Choose the output filter components to meet peak
transient requirements. The formula below can be
used to provide an approximate starting point for
capacitor choice, but will be inadequate to calculate
actual values.
100 k
D VPEAK + ( D I D T)
ESL ) D I
ESR
Ideally the output filter should be simulated with
models including ESR, ESL, circuit board parasitics
Figure 15. External UVLO Circuit
Layout Guidelines
With the fast rise, high output currents of microprocessor
applications, parasitic inductance and resistance should be
considered when laying out the power, filter and feedback
signal sections of the board. Typically, a multi?layer board
with at least one ground plane is recommended. If the layout
is such that high currents can exist in the ground plane
underneath the controller or control circuitry, the ground
plane can be slotted to reroute the currents away from the
and delays due to switching frequency and converter
response. Typically both bulk capacitance
(electrolytic, Oscon, etc.,) and low impedance
capacitance (ceramic chip) will be required. The bulk
capacitance provides “hold up” during the converter
response. The low impedance capacitance reduces
steady state ripple and bypasses the bulk capacitance
during slewing of output current.
2. For inductive current sensing (only) choose the
current sense network RC to provide a 25 mV
minimum ramp during steady state operation.
controller. The slots should typically not be placed between
the controller and the output voltage or in the return path of
R + (VIN * VOUT)
f
VOUT VIN
C 25 mV
the gate drive. Additional power and ground planes or
islands can be added as required for a particular layout.
Output filter components should be placed on wide planes
connected directly to the load to minimize resistive drops
during heavy loads and inductive drops and ringing during
transients. If required, the planes for the output voltage and
return can be interleaved to minimize inductance between
the filter and load.
Then choose the inductor value and inherent
resistance to satisfy L/R L = R × C.
For ideal current sense compensation the ratio of L and
R L is fixed, so the values of L and R L will be a
compromise typically with the maximum value R L
limited by conduction losses or inductor temperature
rise and the minimum value of L limited by ripple
current.
http://onsemi.com
16
相关PDF资料 |
PDF描述 |
|---|---|
| VE-J5L-EY-F1 | CONVERTER MOD DC/DC 28V 50W |
| GBM12DTMD-S664 | CONN EDGECARD 24POS R/A .156 |
| UVK1J222MHD | CAP ALUM 2200UF 63V 20% RADIAL |
| UPM2V330MHD | CAP ALUM 33UF 350V 20% RADIAL |
| GBM12DTMN-S664 | CONN EDGECARD 24POS R/A .156 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CS5301GDWR32G | 功能描述:DC/DC 开关控制器 ANA MULTIPHASE CPUCNTR RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK |
| CS5302 | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:Two−Phase Buck Controller with Integrated Gate Drivers and 4−Bit DAC |
| CS5302/D | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Two-Phase Buck Controller with Integrated Gate Drivers and 4-Bit DAC |
| CS5302GDW28 | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:Two−Phase Buck Controller with Integrated Gate Drivers and 4−Bit DAC |
| CS5302GDWR28 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:ON Semiconductor 功能描述: |
发布紧急采购，3分钟左右您将得到回复。