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参数资料
| 型号： | CS5346-CQZ |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 13/38页 |
| 文件大小： | 0K |
| 描述： | IC ADC AUD 103DB 200KHZ 48LQFP |
| 标准包装： | 250 |
| 位数： | 24 |
| 采样率（每秒）： | 200k |
| 数据接口： | 串行 |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 250mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-LQFP（7x7） |
| 包装： | 管件 |
| 输入数目和类型： | 6 个单端，单极 |
| 产品目录页面： | 755 (CN2011-ZH PDF) |
| 配用： | 598-1790-ND - BOARD EVAL FOR CS5346 |
| 其它名称： | 598-1692 |
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20
DS861PP3
CS5346
5.2.2
Master Mode
As a clock master, LRCK and SCLK will operate as outputs. LRCK and SCLK are internally derived from
MCLK with LRCK equal to Fs and SCLK equal to 64 x Fs as shown in Figure 8.
5.2.3
Slave Mode
In Slave Mode, SCLK and LRCK operate as inputs. The Left/Right clock signal must be equal to the sam-
ple rate, Fs, and must be synchronously derived from the supplied master clock, MCLK.
The serial bit clock, SCLK, must be synchronously derived from the master clock, MCLK, and be equal to
128x, 64x or 48x Fs, depending on the desired speed mode. Refer to Table 3 for required clock ratios.
5.3
High-Pass Filter and DC Offset Calibration
When using operational amplifiers in the input circuitry driving the CS5346, a small DC offset may be driven
into the A/D converter. The CS5346 includes a high-pass filter after the decimator to remove any DC offset
which could result in recording a DC level, possibly yielding clicks when switching between devices in a mul-
tichannel system.
The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation
filter. If the HPFFreeze bit (See “High-Pass Filter Freeze (Bit 1)” on page 29.) is set during normal operation,
the current value of the DC offset for the each channel is frozen and this DC offset will continue to be sub-
tracted from the conversion result. This feature makes it possible to perform a system DC offset calibration
by:
1. Running the CS5346 with the high-pass filter enabled until the filter settles. See the Digital Filter Char-
acteristics section for filter settling time.
2. Disabling the high-pass filter and freezing the stored DC offset.
A system calibration performed in this way will eliminate offsets anywhere in the signal path between the
calibration point and the CS5346.
Single-Speed
Double-Speed
Quad-Speed
SCLK/LRCK Ratio
48x, 64x, 128x
48x, 64x
Table 3. Slave Mode Serial Bit Clock Ratios
÷256
÷128
÷64
÷4
÷2
÷1
00
01
10
00
01
10
LRCK
SCLK
000
001
010
÷1
÷1.5
÷2
011
100
÷3
÷4
MCLK
FM Bits
MCLK Freq Bits
Figure 8. Master Mode Clocking
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CS5346-CQZR | 功能描述:音频模/数转换器 IC IC 103dB 24B 192kHz Stereo Audio ADC RoHS:否 制造商:Wolfson Microelectronics 转换速率: 分辨率: ADC 输入端数量: 工作电源电压: 最大工作温度: 最小工作温度: 安装风格: 封装 / 箱体: 封装: |
| CS5346-DQZ | 功能描述:模数转换器 - ADC 103dB 24Bit 192kHz Stereo Audio ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| CS5346-DQZR | 功能描述:音频数/模转换器 IC 103dB 24Bit 192kHz Stereo Audio ADC RoHS:否 制造商:Texas Instruments 转换器数量: 分辨率:16 bit 接口类型:I2S, UBS 转换速率: 信噪比:98 dB 工作电源电压:5 V DAC 输出端数量:2 工作温度范围:- 25 C to + 85 C 电源电流:23 mA 安装风格:SMD/SMT 封装 / 箱体:TQFP-32 封装:Reel |
| CS5349-000 | 制造商:TE Connectivity 功能描述:4110-10-340812 |
| CS5349-BP | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Analog-to-Digital Converter， 16-Bit |
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