参数资料
型号: CS5361-KSZ
厂商: Cirrus Logic Inc
文件页数: 8/23页
文件大小: 0K
描述: IC ADC AUD 114DB 204KHZ 24-SOIC
标准包装: 31
位数: 24
采样率(每秒): 204k
数据接口: 串行
转换器数目: 2
功率耗散(最大): 235mW
电压电源: 模拟和数字
工作温度: -10°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 24-SOIC(0.295",7.50mm 宽)
供应商设备封装: 24-SOIC
包装: 管件
输入数目和类型: 2 个差分,单极
产品目录页面: 755 (CN2011-ZH PDF)
配用: 598-1547-ND - BOARD EVAL FOR CS5361 STEREO ADC
其它名称: 598-1086-5
CS5361
16
DS467F2
4.0 APPLICATIONS
4.1
Operational Mode/Sample Rate Range Select
The output sample rate, Fs, can be adjusted from 2 kHz to 204 kHz. The CS5361 must be set to the proper speed
mode via the mode pins, M1 and M0. Refer to Table 1.
4.2
System Clocking
The device supports operation in either Master Mode, where the left/right and serial clocks are synchronously gen-
erated on-chip, or Slave Mode, which requires external generation of the left/right and serial clocks. The device also
includes a master clock divider in Master Mode where the master clock will be internally divided prior to any other
internal circuitry when MDIV is enabled, set to logic 1. In Slave Mode, the MDIV pin needs to be disabled, set to logic
0.
4.2.1
Slave Mode
LRCK and SCLK operate as inputs in Slave mode. The left/right clock must be synchronously derived from the mas-
ter clock and be equal to Fs. It is also recommended that the serial clock be synchronously derived from the master
clock and be equal to 64x Fs to maximize system performance. Refer to Table 2 for required clock ratios.
Table 2. CS5361 Slave Mode Clock Ratios
M1 (Pin 14)
M0 (Pin 13)
MODE
Output Sample Rate (Fs)
0
Single Speed Mode
2 kHz - 51 kHz
0
1
Double Speed Mode
50 kHz - 102 kHz
1
0
Quad Speed Mode
100 kHz - 204 kHz
11
Reserved
Table 1. CS5361 Mode Control
Single Speed Mode
Fs = 2 kHz to 51 kHz
Double Speed Mode
Fs = 50 kHz to 102 kHz
Quad Speed Mode
Fs = 100 kHz to 204 kHz
MCLK/LRCK Ratio
256x, 512x
128x, 256x
128x
SCLK/LRCK Ratio
32x, 64x, 128x
32x, 64x
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