参数资料
型号: CS5464-IS
厂商: Cirrus Logic Inc
文件页数: 28/46页
文件大小: 0K
描述: IC PWR/ENERGY METER 3CH 28-SSOP
标准包装: 47
输入阻抗: 30 千欧
测量误差: 0.1%
电压 - 高输入/输出: 0.8V
电压 - 低输入/输出: 0.2V
电流 - 电源: 3.5mA
电源电压: 4.75 V ~ 5.25 V
测量仪表类型: 单相
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-SSOP(0.209",5.30mm 宽)
供应商设备封装: 28-SSOP
包装: 管件
配用: 598-1554-ND - BOARD EVAL FOR CS5464 ADC
其它名称: 598-1193-5
CS5464
8. REGISTER DESCRIPTIONS
1. “Default” = bit states after power-on or reset
2. DO NOT write a “1” to any unpublished register bit.
3. DO NOT write to any unpublished register address.
8.1 Page Register
8.1.1 Page – Address: 31, Write-only, can be written from ANY page.
MSB
LSB
2
2 6
2
5
2
4
2
3
2
2
1
2 0
Default = 0
Register Read and Write commands contain only 5 address bits. But the internal address bus of the CS5464 is
12 bits wide. Therefore, registers are organized into “Pages”. There are 128 pages of 32 registers each. The
Page register provides the 7 high-order address bits and selects one of the 128 register pages. Not all pages
are used,
Page is a write-only integer containing 7 bits.
8.2 Page 0 Registers
8.2.1 Configuration (Config) – Address: 0
23
PC7
15
EWA
7
-
22
PC6
14
-
6
-
21
PC5
13
-
5
-
20
PC4
12
IMODE
4
iCPU
19
PC3
11
IINV
3
K3
18
PC2
10
-
2
K2
17
PC1
9
-
1
K1
16
PC0
8
-
0
K0
Default = 1 (K=1)
28
PC[7:0]
EWA
IMODE, IINV
iCPU
K[3:0]
Phase compensation for channel 1. Sets a delay in voltage, relative to current. Phase is signed
and in the range of -1.0 ? value ? 1.0 sample (OWR) intervals.
Allows the E1 and E2 pins to be configured as open-drain outputs.
0 = Normal Outputs
1 = Open-drain Outputs
Interrupt configuration. Selects INT pin behavior.
00 = Low Logic Level When Asserted
01 = High Logic Level When Asserted
10 = Low-going Pulse on New Interrupt
11 = High-going Pulse on New Interrupt
Inverts the CPUCLK output.
0 = Default
1 = Invert CPUCLK.
Clock divider. Divides MCLK by K to generate internal clock DCLK. (DCLK = MCLK/K). K is
unsigned and in the range of 1 to 16. When zero, K = 16. At reset, K = 1.
DS682F3
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