参数资料
型号: CS5524-ASZR
厂商: Cirrus Logic Inc
文件页数: 3/56页
文件大小: 0K
描述: IC ADC 24BIT 4CH 24-SSOP
标准包装: 1,000
位数: 24
数据接口: 串行
转换器数目: 1
功率耗散(最大): 14.8mW
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-SSOP(0.209",5.30mm 宽)
供应商设备封装: 24-SSOP
包装: 带卷 (TR)
输入数目和类型: 4 个差分,单极;4 个差分,双极
配用: 598-1012-ND - EVAL BOARD FOR CS5524 ADC
CS5521/22/23/24/28
DS317F8
11
SWITCHING CHARACTERISTICS (T
A = 25° C; VA+ = 5 V ±5%; VD+ = 3.0 V ±10% or 5 V ±5%;
Levels: Logic 0 = 0 V, Logic 1 = VD+; CL = 50 pF.))
Notes: 25. Device parameters are specified with a 32.768 kHz clock; however, clocks up to 200 kHz
(CS5522/24/28) or 130 kHz (CS5521/23) can be used for increased throughput.
26. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.
27. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an
external clock source.
28. Applicable when SCLK is continuously running.
Specifications are subject to change without notice.
Parameter
Symbol
Min
Typ
Max
Unit
Master Clock Frequency
(Note 25)
External Clock or Internal Oscillator (CS5522/24/28)
(CS5521/23)
XIN
30
32.768
200
130
kHz
Master Clock Duty Cycle
40
-
60
%
Rise Times
(Note 26)
Any Digital Input Except SCLK
SCLK
Any Digital Output
trise
-
50
1.0
100
-
s
ns
Fall Times
(Note 26)
Any Digital Input Except SCLK
SCLK
Any Digital Output
tfall
-
50
1.0
100
-
s
ns
Start-up
Oscillator Start-up Time
XTAL = 32.768 kHz
(Note 27)
tost
-500
-
ms
Serial Port Timing
Serial Clock Frequency
SCLK
0
-
2
MHz
SCLK Falling to CS Falling for continuous running SCLK
(Note 28)
t0
100
-
ns
Serial Clock
Pulse Width High
Pulse Width Low
t1
t2
250
-
ns
SDI Write Timing
CS Enable to Valid Latch Clock
t3
50
-
ns
Data Set-up Time prior to SCLK rising
t4
50
-
ns
Data Hold Time After SCLK Rising
t5
100
-
ns
SCLK Falling Prior to CS Disable
t6
100
-
ns
SDO Read Timing
CS to Data Valid
t7
--
150
ns
SCLK Falling to New Data Bit
t8
--
150
ns
CS Rising to SDO Hi-Z
t9
--
150
ns
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