参数资料
型号: CS7654-KQ
厂商: CIRRUS LOGIC INC
元件分类: 消费家电
英文描述: CCD COLOR SPACE PROCESSOR WITH ANALOG OUTPUT
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
封装: 10 X 10 X 1.40 MM, TQFP-64
文件页数: 56/62页
文件大小: 1028K
代理商: CS7654-KQ
CS7654
56
Power Supply Connection
VDD - Power Supply, PINS 8, 40.
Positive digital supplies. Nominally +5 volts.
VDD_BG, VDD_DAC, VDD_PLL - Power Supply, PINS 50, 55, 61.
Positive analog supplies. Nominally +5 volts. Respectively Bandgap, DAC and PLL supplies.
GND - Digital Ground, PINS 9, 39.
Digital ground supplies.
GND_BG, GND_DAC, GND_PLL - Digital Ground, PINS 49, 54, 62.
Digital ground supplies. Respectively Bandgap, DAC and PLL ground.
Input Data and Clocks
DIN[9:0] - Digital Mosaic Inputs, Pins [15:10, 7:3].
CMOS level mosaic coded CCD input data from CCD digitizer
CLKIN_GRG - Mosaic Input Data Clock, PIN 43.
Main system input clock, used to strobe incoming digital CCD mosaic data. The CLKIN
frequency is identical to the mosaic input data rate.
XTAL_IN/CLKIN2X - Mosaic Input Data Interpolation Clock, PIN 59.
Mosaic input data interpolation clock or crystal oscillator input.
CLKOUT_GRG - CCD Sample Clock, PIN 60.
This clock is scaled by the internal PLL and is equal to the CLKIN2X frequency divided by the
scaling ratio. This clock is intended to connect to the CS7615 master clock pin (pin 32).
XTAL_OUT – Crystal oscillator output, PIN 58.
When using the internal crystal oscillator, connect the external crystal to the XTAL_OUT and
CLKIN2X pins. If unused leave floating.
HREFIN - Horizontal Input Timing Reference, PIN 37.
Active low horizontal input timing reference. Used to synchronize the output timing signals
with the incoming mosaic data and timing. When used with CCD digitizers like the CS7615
which imbed the necessary timing signals in the data stream, the HREFIN signal is not needed.
VREFIN - Vertical Input Timing Reference, PIN 38.
Active low vertical input timing reference. Used to synchronize the output timing signals with
the incoming mosaic data and timing. When used with CCD digitizers like the CS7615 which
embed the necessary timing signals in the data stream, the VREFIN signal is not needed.
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