参数资料
型号: CSIX-LEV1-O4-N1
厂商: Lattice Semiconductor Corporation
文件页数: 10/24页
文件大小: 0K
描述: INTERFACE IP CSIX LEVEL 1 ORCA 4
标准包装: 1
系列: *
其它名称: CSIXLEV1O4N1
Lattice Semiconductor
Detailed Register Descriptions (Continued)
CSIX Level 1 IP Core User’s Guide
Address: 0x8010
Name: Force V Parity Error Register
D7
D6
D5
D4
D3
Force
VPERR_3
D2
Force
VPERR_2
D1
Force
VPERR_1
D0
Force
VPERR_0
Default value: 0x00
Description:
Force_VPERR_N
Address: 0x8040
Mode: Read/Write
When high, the vertical parity checker on channel N is forced to detect a parity error. Note this
bit is not self clearing. The bit must be written to zero to deassert the associated error condi-
tion.
Name: In_Data_Lo_Watermark_0
D7
D6
D5
D4
D3
D2
D1
D0
IBD_LOW_WMARK_0
Default value: 0x08
Description:
IBD_LOW_WMARK_0
Address: 0x8044
Mode: Read/Write
Channel 0, low watermark for inbound data FIFO. This value represents the number of FIFO
words (4 bytes) that assert the FIFO low watermark. When the number of words in the FIFO
exceeds this value, the FIFO’s frame available signal asserts.
Name: In_Control_Lo_Watermark_0
D7
D6
D5
D4
D3
D2
D1
D0
IBC_LOW_WMARK_0
Default value: 0x08
Description:
IBC_LOW_WMARK_0
Address: 0x8048
Mode: Read/Write
Channel 0, low watermark for inbound control FIFO. This value represents the number of FIFO
words (4 bytes) that assert the FIFO low watermark. When the number of words in the FIFO
exceeds this value, the FIFO’s frame available signal asserts.
Name: In_Data_Hi_Watermark_0
D7
D6
D5
D4
D3
D2
D1
D0
IBD_HI_WMARK_0
Default value: 0x3f
Description:
IBD_HI_WMARK_0
Mode: Read/Write
Channel 0, high watermark for inbound data FIFO. This value represents the number of FIFO
words (4 bytes) that assert the FIFO high watermark. When the number of words in the FIFO
exceeds this value, the FIFO’s PARTIAL_FULL signal asserts.
10
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