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参数资料
| 型号： | CSIX-LEV1-O4-N1 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 21/24页 |
| 文件大小： | 0K |
| 描述： | INTERFACE IP CSIX LEVEL 1 ORCA 4 |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | CSIXLEV1O4N1 |
Lattice Semiconductor
CSIX Level 1 IP Core User’s Guide
Figure 10. Example Application
Generic FIFO Bridge Loopback
User Application
External
CSIX
Interface
C6_TOP
Internal
Generic FIFO
Bridge
Interface
Generic
FIFO Bridge
Loopback
Internal
Register
Interface
External
SYSBUS
PowerPC
Interface
The following Verilog ?les for CSIX Level 1 core are provided:
? csix_lev1_o4_01_001.v: top level for the CSIX Level 1 IP core
? sine_loopback.v: example user application for CSIX Level 1 IP core
? mpi_synth.v: top level for ORCA PowerPC-to-Register Interface module
? lb_top_1.v: top-level module that uses ties all the application components together
Users can use the CSIX top level as a black box in system designs. Users may also use lb_top_1.v as a template
for an application. However, all inappropriate modules (e.g. the Generic FIFO Bridge loopback module) must be
replaced by the real application modules. Also, any invalid internal signal names (e.g. Generic FIFO Bridge inter-
face, register interface) must be replaced with the actual names from the real application.
Black Box Considerations
Since the core is delivered as a gate-level netlist, the synthesis software will not re-synthesize the internal nets of
the core. For more information regarding Synplify’s black box declaration, please refer to the Instantiating Black
Boxes in Verilog section of the Synplify Reference Manual.
The core implementation consists of synthesis and place and route sections. Each section is described below. Two
synthesis tools, Synplicity ? Synplify ? and LeonardoSpectrum?, are included in Lattice’s ispLEVER software for
seamless processing of designs. The current IP cores are being tested with EDIF ?ow. The following are the step-
by-step procedures for each synthesis tool to generate the EDIF netlist containing the IP core as a black box.
Synthesis using Synplicity’s Synplify
The step-by-step procedure provided below describes how to run synthesis using Synplify.
1. Launch the Synplify synthesis tool.
2. Select -> Open Project -> Existing Project
navigate to select the following ?le: eval\synthesis\synplicity\user_application\top_001.prj
3. Click on the RUN button. This starts the synthesis process. When complete, the resulting synthesized design
resides in the ?le: TOP.edn.
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相关PDF资料 |
PDF描述 |
|---|---|
| CSIX-PI40-O4-N1 | INTERFACE IP CSIX TO PI40 ORCA 4 |
| CT0805S14BAUTOG | VARISTOR 14VRMS 0805 SMD AUTO |
| CT1206K17G | VARISTOR 17VRMS 1206 SMD |
| CTB-B-B-15 | CIRCUIT BREAKER ROCKER 15A SP BK |
| CU3225K17AUTOG2 | VARISTOR AUTO 17VRMS 3225 SMD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CSIX-PI40-O4-N1 | 功能描述:输入/输出控制器接口集成电路 CSIX to PI40 RoHS:否 制造商:Silicon Labs 产品: 输入/输出端数量: 工作电源电压: 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:QFN-64 封装:Tray |
| CSJ-100 | 制造商:GREENLEE TOOL CO 功能描述:Digital Open Jaw Clampmeter 制造商:Greenlee Textron Inc 功能描述:CLAMPMETER |
| CSJ-23 | 功能描述:EXTRACTION TOOL FOR SCS RoHS:否 类别:工具 >> 插入，抽取 系列:* 标准包装:1 系列:* 其它名称:0011-03-00080011-03-0008-E00110300080011030008-E11-03-0008-E1103000811030008-EQ4729393AT0980176A |
| CSJ32C1 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:HC-49/US SMD Microprocessor Crystals |
| CSJ32C3 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:HC-49/US SMD Microprocessor Crystals |
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