参数资料
型号: CSIX-PI40-O4-N1
厂商: Lattice Semiconductor Corporation
文件页数: 9/23页
文件大小: 0K
描述: INTERFACE IP CSIX TO PI40 ORCA 4
标准包装: 1
系列: *
其它名称: CSIXPI40O4N1
Lattice Semiconductor
CSIX-to-PI40 IP Core User’s Guide
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Multicast ID Cframe mapping:
- RES = 0
- EBP = 1 if CSIX Ready = 0 or outbound FIFOs exceed high watermark, else EBP = 0
- TRCLASS = top 3 bits of CSIX Class
- MC = 1
- PSW_ID = provisionable
- RQN = 0
- MCTAG = bottom 20 bits of CSIX Multicast ID
If the CSIX Ready bits (CRdy or DRdy) go low (0) or the outbound FIFOs exceed their high watermark, Egress
Backpressure (EBP) is asserted in the ingress cells.
If there are no Unicast or Multicast cells, Idle cells are generated as follows:
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Idle cell format with egress back pressure:
- RES = 0
- EBP = 1 if CSIX Ready = 0 or outbound FIFOs exceed high watermark, else EBP = 0
- TRCLASS = 111
- MC = 0
- PSW_ID = provisionable
- RQN = 0
- DEST/MCTAG = 0
PI40 Cells to ORSO Embedded Core
PI40 Unicast or Multicast cells are passed to the 2-link ORSO Output Port Controller (OPC2) whenever available.
PI40 Idle cells are sent when no valid data cells are available. The OPC2 automatically prepends PI40 Link Header
Byte and appends PI40 BIP8 to each PI40 cell. The OPC2 manages cell transmission on the corresponding SER-
DES links. Complete details on the OPC2 interface and functionality are given in the ORCA ORSO82G5 data
sheet.
Egress (PI40-to-CSIX) Direction Data Flow
In the egress direction, Unicast and Multicast Cframes are extracted from PI40 cells received on the SERDES links
and written to the CSIX-L1 Outbound Data FIFO and then transmitted on the CSIX interface. Flow control informa-
tion extracted from the egress PI40 cells is used to generate CSIX Flow Control Cframes that are written to the
CSIX Outbound Control FIFO and then transmitted on the CSIX interface. The CSIX/PI40 Bridge IP supports
Cframes mapped to PI40 FOPI Format 1 cells as shown in Figure 7.
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