- 您现在的位置：买卖IC网 > PDF目录17034 > CWMPCEVB5200BE (Freescale Semiconductor)BOARD MPC5200B W/256MB PDF资料下载
参数资料
| 型号： | CWMPCEVB5200BE |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 63/72页 |
| 文件大小： | 0K |
| 描述： | BOARD MPC5200B W/256MB |
| 标准包装： | 1 |
| 类型： | MPU |
| 适用于相关产品： | MPC5200B |
| 所含物品： | 板 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页当前第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页
MPC5200B Data Sheet, Rev. 4
66
Freescale Semiconductor
3.3.2
Pull-up Requirements for the PCI Control Lines
If the PCI interface is NOT used (and internally disabled) the PCI control pins must be terminated as indicated by the PCI Local
Bus specification. This is also required for MOST/Graphics and Large Flash Mode.
PCI control signals always require pull-up resistors on the motherboard (not the expansion board) to ensure that they contain
stable values when no agent is actively driving the bus. This includes PCI_FRAME, PCI_TRDY, PCI_IRDY, PCI_DEVSEL,
PCI_STOP, PCI_SERR, PCI_PERR, and PCI_REQ.
3.3.3
Pull-up/Pull-down Requirements for MEM_MDQS Pins (SDRAM)
The MEM_MDQS[3:0] signals are not used with SDR memories and require pull-up or pull-down resistors in SDRAM mode.
3.3.4
.
Pull-up/Pull-down Requirements for MEM_MDQS Pins (DDR 16-bit
Mode)
The MEM_MDQS[1:0] signals are not used in DDR 16-bit mode and require pull-down resistors.
3.4
JTAG
The MPC5200B provides the user an IEEE 1149.1 JTAG interface to facilitate board/system testing. It also provides a Common
On-Chip Processor (COP) Interface, which shares the IEEE 1149.1 JTAG port. The COP Interface provides access to the
MPC5200B's embedded Freescale (formerly Motorola) MPC603e e300 processor. This interface provides a means for
executing test routines and for performing software development and debug functions.
3.4.1
JTAG_TRST
Boundary scan testing is enabled through the JTAG interface signals. The JTAG_TRST signal is optional in the IEEE 1149.1
specification but is provided on all processors that implement the PowerPC architecture. To obtain a reliable power-on reset
performance, the JTAG_TRST signal must be asserted during power-on reset.
3.4.1.1
JTAG_TRST and PORRESET
The JTAG interface can control the direction of the MPC5200B I/O pads via the boundary scan chain. The JTAG module must
be reset before the MPC5200B comes out of power-on reset; do this by asserting JTAG_TRST before PORRESET is released.
For more details refer to the Reset and JTAG Timing Specification.
Figure 53. PORRESET vs. JTAG_TRST
3.4.1.2
Connecting JTAG_TRST
The wiring of the JTAG_TRST depends on the existence of a board-related debug interface. (see below)
JTAG_TRST
PORRESET
Required assertion of JTAG_TRST
Optional assertion of JTAG_TRST
相关PDF资料 |
PDF描述 |
|---|---|
| 0210490246 | CABLE JUMPER 1.25MM .178M 18POS |
| 0210490245 | CABLE JUMPER 1.25MM .178M 18POS |
| 0210390953 | CABLE JUMPER 1MM .152M 25POS |
| RBC08DRYI-S734 | CONN EDGECARD 16POS DIP .100 SLD |
| LGU2E471MELA | CAP ALUM 470UF 250V 20% SNAP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CWMPCEVB5200BE | 制造商:Freescale Semiconductor 功能描述:MPC5200B BOARD W/ 256MB |
| CWMPH1 | 功能描述:电线导管 In-Cabinet Horizontal Cable Manager Fron RoHS:否 制造商:Panduit 类型:Slotted SideWall Open finger design wiring cut 材料:Polypropylene 颜色:Light Gray 大小: 最大光束直径: 抗拉强度: 外部导管宽度:25 mm 外部导管高度:25 mm |
| CWMPH1Y | 制造商:Panduit Corp 功能描述:PANDUIT |
| CWMPHF1 | 功能描述:电线导管 In-Cabinet Horizontal Cable Manager Fron RoHS:否 制造商:Panduit 类型:Slotted SideWall Open finger design wiring cut 材料:Polypropylene 颜色:Light Gray 大小: 最大光束直径: 抗拉强度: 外部导管宽度:25 mm 外部导管高度:25 mm |
| CWMPV2318 | 功能描述:电线导管 In-Cabinet Vertical Cable Manager 18 RU RoHS:否 制造商:Panduit 类型:Slotted SideWall Open finger design wiring cut 材料:Polypropylene 颜色:Light Gray 大小: 最大光束直径: 抗拉强度: 外部导管宽度:25 mm 外部导管高度:25 mm |
发布紧急采购，3分钟左右您将得到回复。