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| 型号： | CY2077 |
| 厂商： | Cypress Semiconductor Corp. |
| 英文描述： | High-accuracy EPROM Programmable Single-PLL Clock Generator(高精度EPROM，可编程单PLL时钟发生器) |
| 中文描述： | 高精度可编程存储器单PLL时钟发生器（高精度存储器，可编程单锁相环时钟发生器） |
| 文件页数： | 3/13页 |
| 文件大小： | 268K |
| 代理商： | CY2077 |
CY2077
Document #: 38-07210 Rev. *B
Page 3 of 13
Device Functionality: Output Frequencies
Absolute Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Supply Voltage..................................................
–
0.5 to +7.0V
Input Voltage...........................................
–
0.5V to V
DD
+0.5V
Storage Temperature (Non-Condensing)....
–
55
°
C to +150
°
C
Junction Temperature................................................. 150
°
C
Static Discharge Voltage.......................................... > 2000V
(per MIL-STD-883, Method 3015)
Symbol
Fo
Description
Condition
V
DD
= 4.5
–
5.5V
V
DD
= 3.0
–
3.6V
Min.
0.39
0.39
Max.
133
100
Unit
MHz
MHz
Output frequency
Operating Conditions for Commercial Temperature Device
Parameter
V
DD
T
A
C
TTL
Description
Min.
3.0
0
Max.
5.5
+70
Unit
V
°
C
Supply Voltage
Operating Temperature, Ambient
Max. Capacitive Load on outputs for TTL levels
V
DD
= 4.5
–
5.5V, Output frequency = 1
–
40 MHz
V
DD
= 4.5
–
5.5V, Output frequency = 40
–
125 MHz
V
DD
= 4.5
–
5.5V, Output frequency = 125
–
133 MHz
Max. Capacitive Load on outputs for CMOS levels
V
DD
= 4.5
–
5.5V, Output frequency = 1
–
40 MHz
V
DD
= 4.5
–
5.5V, Output frequency = 40
–
125 MHz
V
DD
= 4.5
–
5.5V, Output frequency = 125
–
133 MHz
V
DD
= 3.0
–
3.6V, Output frequency = 1
–
40 MHz
V
DD
= 3.0
–
3.6V, Output frequency = 40
–
100 MHz
Reference Frequency, input crystal with C
load
= 10 pF
Reference Frequency, external clock source
Power-up time for all VDD's to reach minimum specified voltage (power
ramps must be monotonic)
50
25
15
pF
pF
pF
C
CMOS
50
25
15
30
15
30
75
pF
pF
pF
pF
pF
MHz
MHz
X
REF
10
1
t
PU
0.05
50
ms
Electrical Characteristics
T
A
=
0
°
C to +70
°
C
Parameter Description
V
IL
Low-level Input Voltage
Test Conditions
V
DD
= 4.5
–
5.5V
V
DD
= 3.0
–
3.6V
V
DD
= 4.5
–
5.5V
V
DD
= 3.0
–
3.6V
V
DD
= 4.5
–
5.5V, I
OL
= 16 mA
V
DD
= 3.0
–
3.6V, I
OL
= 8 mA
V
DD
= 4.5
–
5.5V, I
OH
=
–
16 mA
V
DD
= 3.0
–
3.6V, I
OH
=
–
8 mA
V
DD
= 4.5
–
5.5V, I
OH
=
–
8 mA
Min.
Typ.
Max.
0.8
0.2V
DD
Unit
V
V
V
V
V
V
V
V
V
V
IH
High-level Input Voltage
2.0
0.7V
DD
V
OL
Low-level Output Voltage
0.4
0.4
V
OHCMOS
High-level Output Voltage,
CMOS levels
High-level Output Voltage,
TTL levels
Input Low Current
Input High Current
Power Supply Current,
Unloaded
Stand-by current
(PD = 0)
Input Pull-Up Resistor
V
DD
–
0.4
V
DD
–
0.4
2.4
V
OHTTL
I
IL
I
IH
I
DD
V
IN
= 0V
V
IN
= V
DD
V
DD
= 4.5
–
5.5V, Output frequency <= 133 MHz
V
DD
= 3.0
–
3.6V, Output frequency <= 100 MHz
V
DD
= 4.5
–
5.5V
V
DD
= 3.0
–
3.6V
V
DD
= 4.5
–
5.5V, V
IN
= 0V
V
DD
= 4.5
–
5.5V, V
IN
= 0.7V
DD
10
5
45
25
100
50
8.0
200
μ
A
μ
A
mA
mA
μ
A
I
DDS[3]
25
10
3.0
100
20
R
UP
1.1
50
M
k
μ
A
I
OE_CLKOUT
CLKOUT Pulldown current V
DD
= 5.0
Note:
3.
If external reference is used, it is required to stop the reference (set reference to LOW) during power down.
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