参数资料
型号: CY2077
厂商: Cypress Semiconductor Corp.
英文描述: High-accuracy EPROM Programmable Single-PLL Clock Generator(高精度EPROM,可编程单PLL时钟发生器)
中文描述: 高精度可编程存储器单PLL时钟发生器(高精度存储器,可编程单锁相环时钟发生器)
文件页数: 6/13页
文件大小: 268K
代理商: CY2077
CY2077
Document #: 38-07210 Rev. *B
Page 6 of 13
t
2
Output Clock Rise Time
Between 0.8
2.0V, V
DD
= 4.5V
5.5V, C
L
= 35 pF
Between 0.8
2.0V, V
DD
= 4.5V
5.5V, C
L
= 15 pF
Between 0.8
2.0V, V
DD
= 4.5V
5.5V, C
L
= 10 pF
Between 0.2V
DD
0.8V
DD
, V
DD
= 4.5V
5.5V, C
L
= 35 pF
Between 0.2V
DD
0.8V
DD
, V
DD
= 3.0V
3.6V, C
L
= 20 pF
Between 0.2V
DD
0.8V
DD
, V
DD
= 3.0V
3.6V, C
L
= 10 pF
Between 0.8V
2.0V, V
DD
= 4.5V
5.5V, C
L
= 35 pF
Between 0.8
2.0V, V
DD
= 4.5V
5.5V, C
L
= 15 pF
Between 0.8
2.0V, V
DD
= 4.5V
5.5V, C
= 10 pF
Between 0.2V
DD
0.8V
DD
, V
DD
= 4.5V
5.5V, C
L
= 35 pF
Between 0.2V
DD
0.8V
DD
, V
DD
= 3.0V
3.6V, C
L
= 20 pF
Between 0.2V
DD
0.8V
DD
, V
DD
= 3.0V
3.6V, C
L
= 10 pF
PWR_DWN pin LOW to HIGH
[5]
1.8
1.2
0.9
3.4
4.0
2.4
1.8
1.2
0.9
3.4
4.0
2.4
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
t
3
Output Clock Fall Time
t
4
Start-up Time Out of
Power-down
Power-down Delay Time
(synchronous setting)
Power-down Delay Time
(asynchronous setting)
Power-up Time
Output Disable Time
(synchronous setting)
Output Disable Time
(asynchronous setting)
Output Enable Time
(always synchronous
enable)
Peak-to-Peak Period
Jitter
1
t
5a
PWR_DWN pin LOW to output LOW
(T= period of output clk)
PWR_DWN pin LOW to output LOW
T/2
T+10
ns
t
5b
10
15
ns
t
6
t
7a
From power on
[5]
OE pin LOW to output high-Z
(T= period of output clk)
OE pin LOW to output high-Z
1
2
ms
ns
T/2
T + 10
t
7b
10
15
ns
t
8
OE pin LOW to HIGH
(T = period of output clk)
T
1.5T +
25ns
ns
t
9
V
DD
= 3.0V
3.6V, 4.5V
5.5V, Fo > 33 MHz, V
CO
> 100 MHz
V
DD
= 3.0V
5.5V, Fo < 33 MHz
80
0.3%
150
1%
ps
% of
F
O
Switching Waveforms
Output Clock Switching Characteristics Industrial
Over the Operating Range
[4]
Parameter
Description
Test Conditions
Min. Typ.
Max. Unit
Duty Cycle Timing (t
1w
, t
1x
, t
1y
)
t1A
t1B
OUTPUT
Output Rise/Fall Time
OUTPUT
t2
V
DD
0V
t3
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