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参数资料
| 型号： | CY2213ZC-2T |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | XO, clock |
| 英文描述： | High-Frequency Programmable PECL Clock Generator |
| 中文描述： | 500 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封装： | 4.40 MM, TSSOP-16 |
| 文件页数： | 2/10页 |
| 文件大小： | 103K |
| 代理商： | CY2213ZC-2T |
CY2213
Document #: 38-07263 Rev. *E
Page 2 of 10
Pin Description
CY2213 Two-Wire Serial Interface
Introduction
The CY2213 has a two-wire serial interface designed for data
transfer operations, and is used for programming the P and Q
values for frequency generation. S
clk
is the serial clock line
controlled by the master device. S
data
is a serial bidirectional
data line. The CY2213 is a slave device and can either read or
write information on the dataline upon request from the master
device.
Figure 1
shows the basic bus connections between master
and slave device. The buses are shared by a number of
devices and are pulled high by a pull-up resistor.
Serial Interface Specifications
Figure 2
shows the basic transmission specification. To begin
and end a transmission, the master device generates a start
signal (S) and a stop signal (P). Start (S) is defined as
switching the S
data
from HIGH to LOW while the S
clk
is at
HIGH. Similarly, stop (P) is defined as switching the S
data
from
LOW to HIGH while holding the S
clk
HIGH. Between these two
signals, data on S
data
is synchronous with the clock on the S
clk
.
Data is allowed to change only at LOW period of clock, and
must be stable at the HIGH period of clock. To acknowledge,
drive the S
data
LOW before the S
clk
rising edge and hold it
LOW until the S
clk
falling edge.
Serial Interface Format
Each slave carries an address. The data transfer is initiated by
a start signal (S). Each transfer segment is 1 byte in length.
The slave address and the read/write bit are first sent from the
master device after the start signal. The addressed slave
device must acknowledge (Ack) the master device. Depending
on the Read/Write bit, the master device will either write data
into (logic 0) or read data (logic 1) from the slave device. Each
time a byte of data is successfully transferred, the receiving
device must acknowledge. At the end of the transfer, the
master device will generate a stop signal (P).
Serial Interface Transfer Format
Figure 2
shows the serial interface transfer format used with
the CY2213. Two dummy bytes must be transferred before the
first data byte. The CY2213 has only three bytes of latches to
store information, and the third byte of data is reserved. Extra
data will be ignored.
Pin Name
VDDX
VSSX
XOUT
XIN
VDD
OE
VSS
SER CLK
SER DATA
VDD
VSS
CLKB
CLK
VSS
VDD
S
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Description
3.3V Power Supply for Crystal Driver
Ground for Crystal Driver
Reference Crystal Feedback
Reference Crystal Input
3.3 V Power Supply (all V
DD
pins must be tied directly on board)
Output Enable, 0 = output disable, 1 = output enable (no internal pull-up)
Ground
Serial Interface Clock
Serial Interface Data
3.3V Power Supply (all V
DD
pins must be tied directly on board)
Ground
LVPECL Output Clock (complement)
LVPECL Output Clock
Ground
3.3V Power Supply (all V
DD
pins must be tied directly on board)
PLL Multiplier Select Input, Pull-up Resistor Internal
Frequency Table
S
M (PLL Multiplier)
x16
Example Input Crystal Frequency
25 MHz
31.25 MHz
15.625 MHz
CLK,CLKB
400 MHz
500 MHz
125 MHz
0
1
x8
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CY2213ZXC-1 | 功能描述:锁相环 - PLL HI FREQUENCY PRGMBLE PECL CLOCK GEN RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| CY2213ZXC-1KN | 制造商:Rochester Electronics LLC 功能描述: 制造商:Cypress Semiconductor 功能描述: |
| CY2213ZXC-1T | 功能描述:锁相环 - PLL HI FREQUENCY PRGMBLE PECL CLOCK GEN RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| CY2213ZXC-2 | 功能描述:锁相环 - PLL HI Freq PECL Clock Generator RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
| CY2213ZXC-2T | 功能描述:锁相环 - PLL HI Freq PECL Clock Generator RoHS:否 制造商:Silicon Labs 类型:PLL Clock Multiplier 电路数量:1 最大输入频率:710 MHz 最小输入频率:0.002 MHz 输出频率范围:0.002 MHz to 808 MHz 电源电压-最大:3.63 V 电源电压-最小:1.71 V 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:QFN-36 封装:Tray |
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