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| 型号： | CY28346ZXC-2 |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 7/19页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK DIFF OUT CK408 56TSSOP |
| 标准包装： | 35 |
| 类型： | * |
| PLL： | 是 |
| 输入： | 晶体 |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:21 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 200MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | * |
| 封装/外壳： | * |
| 供应商设备封装： | * |
| 包装： | * |
CY28346-2
...................... Document #: 38-07509 Rev. *B Page 15 of 19
Tskew
Any CPU to CPU
Clock Skew
100
ps
Tccj
CPU Cycle to Cycle
Jitter
150
ps
Tr/Tf
CPUT and CPUC
Rise and Fall Times
175
700
175
700
175
700
175
700
ps
Rise/Fall Matching
20%
DeltaTr
Rise Time Variation
125
ps
DeltaTf
Fall Time Variation
125
ps
Vcross
Crossing Point
Voltage at 0.7V
Swing
280
430
280
430
280
430
280
430
mV
CPU at 1.0V Timing
Tdc
CPUT and CPUC
Duty Cycle
45
55
45
55
45
55
45
55
%
Tperiod
CPUT and CPUC
Period
14.85
15.3
9.85
10.2
7.35
7.65
4.85
5.1
nS
Tskew
Any CPU to Any
CPU Clock Skew
100
pS
Tccj
CPU Cycle to Cycle
Jitter
150
pS
Differential
Tr/Tf
CPUT and CPUC
Rise and Fall Times
175
467
175
467
175
467
175
467
ps
SE-
DeltaSlew
Absolute Single-
ended Rise/Fall
Waveform
Symmetry
325
ps
Vcross
Cross Point at 1.0V
swing
510
760
510
760
510
760
510
760
mV
3V66
Tdc
3V66 Duty Cycle
45
554555
45
55
45
55
%
Tperiod
3V66 Period
15.0
15.3
15.0
15.3
15.0
15.3
15.0
15.3
ns
Thigh
3V66 High Time
4.95
ns
Tlow
3V66 Low Time
4.55
ns
Tr / Tf
3V66 Rise and Fall
Times
0.5
2.0
0.5
2.0
0.5
2.0
0.5
2.0
ns
Notes:
14. Measured from Vol = 0.175V to Voh = 0.525V.
15. Determined as a fraction of 2*(Trise – Tfall)/ (Trise + Tfall).
16. Measurement taken from differential waveform, from –0.35V to +0.35V.
17. Measurements taken from common mode waveforms, measure rise/fall time from 0.41 to 0.86V. Rise/fall time matching is defined as “the instantaneous difference
between maximum clk rise (fall) and minimum clk# fall (rise) time or minimum clk rise (fall) and maximum clk# fall (rise) time”. This parameter is designed form
waveform symmetry.
18. Measured in absolute voltage, i.e. single-ended measurement.
19. THIGH is measured at 2.4V for non host outputs.
20. TLOW is measured at 0.4V for all outputs.
21. Probes are placed on the pins, and measurements are acquired between 0.4V and 2.4V for 3.3V signals (see test and measurement set-up section of this data
sheet).
AC Parameters (VDD = VDDA = 3.3V ±5%) (continued)
Parameter
Description
66 MHz
100 MHz
133 MHz
200 MHz
Unit
Notes
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
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