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参数资料
| 型号： | CY28353OXC-2 |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 1/9页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK DIFF/DRIVER PLL 28TSSOP |
| 标准包装： | 47 |
| 类型： | 扇出缓冲器（分配） |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:6 |
| 差分 - 输入:输出： | 是/是 |
| 输入： | 时钟 |
| 输出： | 时钟 |
| 频率 - 最大： | 170MHz |
| 电源电压： | 2.375 V ~ 2.625 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | * |
| 封装/外壳： | * |
| 供应商设备封装： | * |
| 包装： | * |
Differential Clock Buffer/Driver
CY28353-2
.......................... Document #: 38-07372 Rev. *B Page 1 of 9
400 West Cesar Chavez, Austin, TX 78701
1+(512) 416-8500
1+(512) 416-9669
www.silabs.com
Features
Phase-locked loop (PLL) clock distribution for double
data rate synchronous DRAM applications
Distributes one differential clock input to six differential
outputs
External feedback pins (FBINT, FBINC) are used to
synchronize the outputs to the clock input
Conforms to the DDRI specification
Spread Aware for electromagnetic interference (EMI)
reduction
28-pin SSOP package
Description
This PLL clock buffer is designed for 2.5 VDD and 2.5 AVDD
operation and differential data input and output levels.
This device is a zero delay buffer that distributes a differential
clock input pair (CLKINT, CLKINC) to six differential pairs of
clock outputs (CLKT[0:5], CLKC[0:5]) and one differential pair
feedback clock outputs (FBOUTT, FBOUTC). The clock
outputs are controlled by the input clocks (CLKINT, CLKINC)
and the feedback clocks (FBINT, FBINC).
The two-line serial bus can set each output clock pair
(CLKT[0:5], CLKC[0:5]) to the Hi-Z state. When AVDD is
grounded, the PLL is turned off and bypassed for test
purposes.
The PLL in this device uses the input clocks (CLKINT,
CLKINC) and the feedback clocks (FBINT, FBINC) to provide
high-performance, low-skew, low–jitter output differential
clocks.
Block Diagram
Pin Configuration
28 pin SSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
CLKT5
FBINC
FBOUTT
CLKT3
CLKC3
GND
FBOUTC
FBINT
CLKC5
CLKC4
CLKT4
VDD
SDATA
CLKC0
VDD
CLKINT
AVDD
VDD
CLKT2
CLKC2
AGND
CLKINC
CLKT0
CLKT1
CLKC1
GND
SCLK
CY28353-
2
Serial
Interface
Logic
SDATA
SCLK
CLKT0
FBOUTT
FBOUTC
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKC3
CLKT3
CLKC4
CLKT4
CLKC5
CLKT5
PLL
FBINC
FBINT
CLKINT
AVDD
CLKINC
10
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CY28353OXC-2T | 功能描述:时钟缓冲器 Differential clock Buffer/Driver RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| CY28354-400 | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:210-MHz 24-Output Buffer for 4-DDR DIMMS for VIA Chipsets Support |
| CY28354OXC-400 | 功能描述:时钟缓冲器 273MHz Output Buffer for 4 DDR DIMMs RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| CY28354OXC-400T | 功能描述:时钟缓冲器 273MHz Output Buffer for 4 DDR DIMMs RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| CY28358 | 制造商:SPECTRALINEAR 制造商全称:SPECTRALINEAR 功能描述:200-MHz Differential Clock Buffer/Driver |
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