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参数资料
| 型号： | CY28353OXC-2 |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 2/9页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK DIFF/DRIVER PLL 28TSSOP |
| 标准包装： | 47 |
| 类型： | 扇出缓冲器（分配） |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:6 |
| 差分 - 输入:输出： | 是/是 |
| 输入： | 时钟 |
| 输出： | 时钟 |
| 频率 - 最大： | 170MHz |
| 电源电压： | 2.375 V ~ 2.625 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | * |
| 封装/外壳： | * |
| 供应商设备封装： | * |
| 包装： | * |
CY28353-2
.......................... Document #: 38-07372 Rev. *B Page 2 of 9
Pin Description [1]
Pin Number
Pin Name
I/O
Pin Description
Electrical Characteristics
8CLKINT
I
Complementary Clock Input.
LV Differential Input
9CLKINC
I
Complementary Clock Input.
21
FBINC
I
Feedback Clock Input. Connect to
FBOUTC for accessing the PLL.
Differential Input
20
FBINT
I
Feedback Clock Input. Connect to
FBOUTT for accessing the PLL.
2,4,13,17,24,26
CLKT(0:5)
O
Clock Outputs.
Differential Outputs
1,5,14,16,25,27
CLKC(0:5)
O
Clock Outputs.
19
FBOUTT
O
Feedback Clock Output. Connect to
FBINT for normal operation. A bypass
delay capacitor at this output will control
Input Reference/Output Clocks phase
relationships.
Differential Output
18
FBOUTC
O
Feedback Clock Output. Connect to
FBINC for normal operation. A bypass
delay capacitor at this output will control
Input Reference/Output Clocks phase
relationships.
7SCLK
I, PU Serial Clock Input. Clocks data at
SDATA into the internal register.
Data Input for the two-line serial
bus
22
SDATA
I/O,
PU
Serial Data Input. Input data is clocked
to the internal register to enable/disable
individual outputs. This provides flexi-
bility in power management.
Data Input and Output for the
two-line serial bus
3,12,23
VDD
2.5V Power Supply for Logic.
2.5V Nominal
10
AVDD
2.5V Power Supply for PLL.
2.5V Nominal
6,15,28
GND
Ground.
11
AGND
Analog Ground for PLL.
Function Table
Inputs
Outputs
PLL
VDDA
CLKINT
CLKINC
CLKT(0:5)[2]
CLKC(0:5)[2]
FBOUTT
FBOUTC
GND
L
H
L
H
L
H
BYPASSED/OFF
GND
H
L
H
L
H
L
BYPASSED/OFF
2.5V
L
H
L
H
L
H
On
2.5V
H
L
H
L
H
L
On
2.5V
< 20 MHz
Hi-Z
Off
Notes:
1. A bypass capacitor (0.1
F) should be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins their
high-frequency filtering characteristic will be cancelled by the lead inductance of the traces.
2. Each output pair can be three-stated via the two-line serial interface.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CY28353OXC-2T | 功能描述:时钟缓冲器 Differential clock Buffer/Driver RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| CY28354-400 | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:210-MHz 24-Output Buffer for 4-DDR DIMMS for VIA Chipsets Support |
| CY28354OXC-400 | 功能描述:时钟缓冲器 273MHz Output Buffer for 4 DDR DIMMs RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| CY28354OXC-400T | 功能描述:时钟缓冲器 273MHz Output Buffer for 4 DDR DIMMs RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| CY28358 | 制造商:SPECTRALINEAR 制造商全称:SPECTRALINEAR 功能描述:200-MHz Differential Clock Buffer/Driver |
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