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参数资料
| 型号： | CY28409OC |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 14/16页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK CK409GRANTSDALE 56TSSOP |
| 标准包装： | 26 |
| 类型： | * |
| PLL： | 是 |
| 输入： | 晶体 |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:21 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 400MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | * |
| 封装/外壳： | * |
| 供应商设备封装： | * |
| 包装： | * |
CY28409
........................Document #: 38-07445 Rev. *D Page 7 of 16
Crystal Recommendations
The CY28409 requires a Parallel Resonance Crystal.
Substituting a series resonance crystal will cause the
CY28409 to operate at the wrong frequency and violate the
ppm specification. For most applications there is a 300-ppm
frequency shift between series and parallel crystals due to
incorrect loading.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, the total capacitance
the crystal will see must be considered to calculate the appro-
priate capacitive loading (CL).
Figure 1 shows a typical crystal configuration using the two
trim capacitors. An important clarification for the following
discussion is that the trim capacitors are in series with the
crystal not parallel. It’s a common misconception that load
capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is not true.
Byte 6: Control Register 6
Bit
@Pup
Name
Description
7
0
Reserved
Reserved, Set = 0
6
0
Reserved
Reserved, Set = 0
5
0
CPUC0, CPUT0
CPUC1, CPUT1
CPUC2, CPUT2
FS_A & FS_B Operation
0 = Normal, 1 = Test mode
4
0
SRCT, SRCC
SRC Frequency Select
0 = 100 MHz, 1 = 200 MHz
3
0
Reserved
Reserved, Set = 0
20
PCIF
PCI
3V66
SRCT,SRCC
CPUT_ITP,CPUC_ITP
Spread Spectrum Enable
0 = Spread Off, 1 = Spread On
1
REF_1
REF_1 Output Enable
0 = Disabled, 1 = Enabled
0
1
REF_0
REF_0 Output Enable
0 = Disabled, 1 = Enabled
Byte 7: Vendor ID
Bit
@Pup
Name
Description
7
0
Revision ID Bit 3
6
1
Revision ID Bit 2
5
0
Revision ID Bit 1
4
0
Revision ID Bit 0
3
1
Vendor ID Bit 3
2
0
Vendor ID Bit 2
1
0
Vendor ID Bit 1
0
Vendor ID Bit 0
Table 6. Crystal Recommendations
Frequency
(Fund)
Cut
Loading Load Cap
Drive
(max.)
Shunt Cap
(max.)
Motional
(max.)
Tolerance
(max.)
Stability
(max.)
Aging
(max.)
14.31818 MHz
AT
Parallel
20 pF
0.1 mW
5 pF
0.016 pF
50 ppm
5 ppm
Figure 1. Crystal Capacitive Clarification
相关PDF资料 |
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| CY28409AZXC | IC CLOCK CK409GRANTSDALE 56TSSOP |
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| VE-B4H-MY-F2 | CONVERTER MOD DC/DC 52V 50W |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CY28409OCT | 功能描述:时钟合成器/抖动清除器 SysClk Intel Grntsdl 865 and 875 chipsets RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| CY28409OCXT | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:Clock Synthesizer with Differential SRC and CPU Outputs |
| CY28409OXC | 功能描述:时钟合成器/抖动清除器 SysClk Intel Grntsdl 865 and 875 chipsets RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| CY28409OXCT | 功能描述:时钟合成器/抖动清除器 SysClk Intel Grntsdl 865 and 875 chipsets RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| CY28409ZC | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:Clock Synthesizer with Differential SRC and CPU Outputs |
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