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| 型号： | CY284108ZXC |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 16/16页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK SERV CK410B 56TSSOP |
| 标准包装： | 35 |
| 类型： | 时钟/频率发生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服务器 |
| 输入： | 晶体 |
| 输出： | HCSL，LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:19 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 400MHz |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 56-TFSOP（0.240"，6.10mm 宽） |
| 供应商设备封装： | 56-TSSOP |
| 包装： | 管件 |
CY284108
........................ Document #: 38-07713 Rev. *B Page 9 of 16
PD (Power-down) Assertion
When PD is sampled high by two consecutive rising edges of
CPUC, all single-ended outputs will be held low on their next
high to low transition and differential clocks must held high or
tri-stated (depending on the state of the control register drive
mode bit) on the next diff clock# high to low transition within 4
clock periods. When the SMBus PD drive mode bit corre-
sponding to the differential (CPU and SRC) clock output of
interest is programmed to ‘0’, the clock outputs are held with
“Diff clock” pin driven high at 2 x Iref, and “Diff clock#” tri-state.
If the control register PD drive mode bit corresponding to the
output of interest is programmed to “1”, then both the “Diff
clock” and the “Diff clock#” are tri-state. Note that Figure 4
shows CPUT = 133 MHz and PD drive mode = ‘1’ for all differ-
ential outputs. This diagram and description is applicable to
valid CPU frequencies 100, 133, 166, 200, 266, 333, and
400 MHz. In the event that PD mode is desired as the initial
power-on state, PD must be asserted high in less than 10
s
after asserting Vtt_PwrGd#.
PD Deassertion
The power-up latency is less than 1.8 ms. This is the time from
the deassertion of the PD pin or the ramping of the power
supply until the time that stable clocks are output from the
clock chip. All differential outputs stopped in a three-state
condition resulting from power down will be driven high in less
than 300
s of PD deassertion to a voltage greater than
200 mV. After the clock chip’s internal PLL is powered up and
locked, all outputs will be enabled within a few clock cycles of
each other. Figure 5 is an example showing the relationship of
clocks coming up.
PD
USB, 48 MHz
SRCT 100 MHz
SRCC 100 MHz
CPUT, 133 MHz
PCI, 33 MHz
REF
CPUC, 133 MHz
Figure 4. Power-down Assertion Timing Waveform
PD
CPUC, 133 MHz
CPUT, 133 MHz
SRCC 100 MHz
USB, 48 MHz
SRCT 100 MHz
Tstable
<1.8 ms
PCI, 33 MHz
REF
Tdrive_PWRDN#
<300
s, >200 mV
Figure 5. Power-down Deassertion Timing Waveform
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| CY284108ZXCT | 功能描述:时钟发生器及支持产品 Server, CK410B RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| CY28410OC | 制造商:SPECTRALINEAR 制造商全称:SPECTRALINEAR 功能描述:Clock Generator for Intel Grantsdale Chipset |
| CY28410OCT | 制造商:SPECTRALINEAR 制造商全称:SPECTRALINEAR 功能描述:Clock Generator for Intel Grantsdale Chipset |
| CY28410OXC | 功能描述:时钟发生器及支持产品 SysClk Intel Lakeprt & Grantsdale Chipset RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| CY28410OXC-2 | 功能描述:时钟发生器及支持产品 SysClk Intel Lakeprt & Grantsdale Chipset RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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