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参数资料
| 型号： | CY28410OXC-2 |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 14/16页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK CK410 GRANTSDALE 56SSOP |
| 标准包装： | 26 |
| 类型： | 时钟/频率发生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服务器 |
| 输入： | 晶体 |
| 输出： | HCSL，LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:21 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 266MHz |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 56-BSSOP（0.295"，7.50mm 宽） |
| 供应商设备封装： | 56-SSOP |
| 包装： | 管件 |
CY28410-2
........................Document #: 38-07747 Rev *.* Page 7 of 16
Crystal Recommendations
The CY28410-2 requires a Parallel Resonance Crystal.
Substituting a series resonance crystal will cause the
CY28410-2 to operate at the wrong frequency and violate the
ppm specification. For most applications there is a 300-ppm
frequency shift between series and parallel crystals due to
incorrect loading.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, the total capacitance
the crystal will see must be considered to calculate the appro-
priate capacitive loading (CL).
Figure 1 shows a typical crystal configuration using the two
trim capacitors. An important clarification for the following
discussion is that the trim capacitors are in series with the
crystal not parallel. It’s a common misconception that load
capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is not true.
3
1
PCIF, SRC, PCI
SW PCI_STP# Function
0=SW PCI_STP assert, 1 = SW PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
2
Externally
selected
CPUT/C
FS_C. Reflects the value of the FS_C pin sampled on power-up
0 = FS_C was low during VTT_PWRGD# assertion
1
Externally
selected
CPUT/C
FS_B. Reflects the value of the FS_B pin sampled on power-up
0 = FS_B was low during VTT_PWRGD# assertion
0
Externally
selected
CPUT/C
FS_A. Reflects the value of the FS_A pin sampled on power-up
0 = FS_A was low during VTT_PWRGD# assertion
Byte 7: Vendor ID
Bit
@Pup
Name
Description
7
0
Revision Code Bit 3
6
0
Revision Code Bit 2
5
1
Revision Code Bit 1
4
0
Revision Code Bit 0
3
1
Vendor ID Bit 3
2
0
Vendor ID Bit 2
1
0
Vendor ID Bit 1
0
Vendor ID Bit 0
Byte 6: Control Register 6 (continued)
Bit
@Pup
Name
Description
Figure 1. Crystal Capacitive Clarification
Table 5. Crystal Recommendations
Frequency
(Fund)
Cut
Loading Load Cap
Drive
(max.)
Shunt Cap
(max.)
Motional
(max.)
Tolerance
(max.)
Stability
(max.)
Aging
(max.)
14.31818 MHz
AT
Parallel
20 pF
0.1 mW
5 pF
0.016 pF
35 ppm
30 ppm
5 ppm
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相关代理商/技术参数 |
参数描述 |
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| CY28410OXC-2T | 功能描述:时钟发生器及支持产品 SysClk Intel Lakeprt & Grantsdale Chipset RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| CY28410OXCT | 功能描述:时钟发生器及支持产品 SysClk Intel Lakeprt & Grantsdale Chipset RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| CY28410ZC | 制造商:SPECTRALINEAR 制造商全称:SPECTRALINEAR 功能描述:Clock Generator for Intel Grantsdale Chipset |
| CY28410ZCT | 制造商:SPECTRALINEAR 制造商全称:SPECTRALINEAR 功能描述:Clock Generator for Intel Grantsdale Chipset |
| CY28410ZXC | 功能描述:时钟发生器及支持产品 SysClk Intel Lakeprt & Grantsdale Chipset RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
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