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参数资料
| 型号： | CY28410ZXC |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 14/17页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK CK410GRANTSDALE 56TSSOP |
| 标准包装： | 35 |
| 类型： | 时钟/频率发生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服务器 |
| 输入： | 晶体 |
| 输出： | HCSL，LVCMOS |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:19 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 266MHz |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 56-TFSOP（0.240"，6.10mm 宽） |
| 供应商设备封装： | 56-TSSOP |
| 包装： | 管件 |
| 其它名称： | SLCY28410ZXC |
CY28410
........................Document #: 38-07593 Rev. *C Page 6 of 17
1
0
SRC1
Allow control of SRC[T/C]1 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
0
Reserved
Reserved, Set = 0
Byte 4: Control Register 4
Bit
@Pup
Name
Description
7
0
Reserved
Reserved, Set = 0
6
0
DOT96[T/C]
DOT_PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Hi-Z
5
0
PCIF2
Allow control of PCIF2 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
4
0
PCIF1
Allow control of PCIF1 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
3
0
PCIF0
Allow control of PCIF0 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with SW PCI_STP#
2
1
Reserved
Reserved, Set = 1
1
Reserved
Reserved, Set = 1
0
1
Reserved
Reserved, Set = 1
Byte 5: Control Register 5
Bit
@Pup
Name
Description
7
0
SRC[T/C][7:0]
SRC[T/C] Stop Drive Mode
0 = Driven when SW PCI_STP# asserted,1 = Hi-Z when PCI_STP#
asserted
6
0
Reserved
Reserved, Set = 0
5
0
Reserved
Reserved, Set = 0
4
0
Reserved
Reserved, Set = 0
3
0
SRC[T/C][7:0]
SRC[T/C] PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
2
0
CPU[T/C]2
CPU[T/C]2 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
1
0
CPU[T/C]1
CPU[T/C]1 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
0
CPU[T/C]0
CPU[T/C]0 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
Byte 6: Control Register 6
Bit
@Pup
Name
Description
7
0
REF/N or Hi-Z Select
1 = REF/N Clock, 0 = Hi-Z
6
0
Test Clock Mode Entry Control
1 = REF/N or Hi-Z mode, 0 = Normal operation
5
0
Reserved
Reserved, Set = 0
4
1
REF
REF Output Drive Strength
0 = Low, 1 = High
3
1
PCIF, SRC, PCI
SW PCI_STP# Function
0=SW PCI_STP assert, 1 = SW PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
Byte 3: Control Register 3 (continued)
Bit
@Pup
Name
Description
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CY28410ZXC-2 | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:Clock Generator for Intel Grantsdale Chipset |
| CY28410ZXC-2T | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:Clock Generator for Intel Grantsdale Chipset |
| CY28410ZXCT | 功能描述:时钟发生器及支持产品 SysClk Intel Lakeprt & Grantsdale Chipset RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56 |
| CY28411 | 制造商:SPECTRALINEAR 制造商全称:SPECTRALINEAR 功能描述:Clock Generator for Intel Alviso Chipset |
| CY28411-1 | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:Clock Generator for Intel Alviso Chipset |
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