参数资料
型号: CY28410ZXC
厂商: Silicon Laboratories Inc
文件页数: 16/17页
文件大小: 0K
描述: IC CLOCK CK410GRANTSDALE 56TSSOP
标准包装: 35
类型: 时钟/频率发生器
PLL:
主要目的: Intel CPU 服务器
输入: 晶体
输出: HCSL,LVCMOS
电路数: 1
比率 - 输入:输出: 1:19
差分 - 输入:输出: 无/是
频率 - 最大: 266MHz
电源电压: 3.135 V ~ 3.465 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 56-TFSOP(0.240",6.10mm 宽)
供应商设备封装: 56-TSSOP
包装: 管件
其它名称: SLCY28410ZXC
CY28410
........................Document #: 38-07593 Rev. *C Page 8 of 17
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
As mentioned previously, the capacitance on each side of the
crystal is in series with the crystal. This mean the total capac-
itance on each side of the crystal must be twice the specified
load capacitance (CL). While the capacitance on each side of
the crystal is in series with the crystal, trim capac-
itors(Ce1,Ce2) should be calculated to provide equal capaci-
tance loading on both sides.
Use the following formulas to calculate the trim capacitor
values fro Ce1 and Ce2.
Figure 1. Crystal Capacitive Clarification
XTAL
Ce2
Ce1
Cs1
Cs2
X1
X2
Ci1
Ci2
Clock Chip
Trace
2.8pF
Trim
33pF
Pin
3 to 6p
Figure 2. Crystal Loading Example
Load Capacitance (each side)
Total Capacitance (as seen by the crystal)
Ce = 2 * CL – (Cs + Ci)
Ce1 + Cs1 + Ci1
1
+
Ce2 + Cs2 + Ci2
1
()
1
=
CLe
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