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参数资料
| 型号： | CY2CC1810SCT |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | 时钟及定时 |
| 英文描述： | 1:10 Clock Fanout Buffer with Output Enable |
| 中文描述： | 2CC SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封装： | 0.300 INCH, SOIC-24 |
| 文件页数： | 3/8页 |
| 文件大小： | 128K |
| 代理商： | CY2CC1810SCT |
COMLINK
SERIES
CY2CC1810
Document #: 38-07055 Rev. *C
Page 3 of 8
Power Supply Characteristics
(See
Figure 1
)
Parameter
ICC
Description
Test Conditions
Min.
Typ.
Max.
50
Unit
uA
Delta I
CC
Quiescent
Power Supply Current
Dynamic Power Supply
Current
(I
DD
@ V
DD
= Max. and V
IN
= V
DD
)
–
(I
DD
@ V
DD
=
Max. and V
IN
= V
DD
–
0.6V)
V
DD
= Max.
Input toggling 50% Duty Cycle,
Outputs Open
V
DD
= Max.
Input toggling 50% Duty Cycle,
Outputs Open fL = 40 MHz
I
CCD
fL= fMAX
OE# = V
DD
0.63
mA/
MHz
I
C
Total Power Supply
Current
fL=100 MHz
OE# = GND
25
mA
High-frequency Parametrics
Parameter
D
J
Description
Jitter, Deterministic
Test Conditions
Min.
Typ
Max
20
Unit
ps
50% duty cycle tW(50
–
50)
The
“
point to point load circuit
”
|Output Jitter
–
Input Jitter|
50% duty cycle tW(50
–
50)
Standard Load Circuit.
50% duty cycle tW(50
–
50)
The
“
point to point load circuit
”
20% duty cycle tW(20
–
80)
The
“
point to point load circuit
”
V
IN
= 3.0V/0.0V V
OUT
= 2.3V/0.4V
The
“
point to point load circuit
”
V
IN
= 2.4V/0.0V V
OUT
= 1.7V/0.7V
The
“
point to point load circuit
”
V
IN
= 3.0V/0.0V F = 100 MHz
V
OUT
= 2.0V/0.8V
The
“
point to point load circuit
”
V
IN
= 2.4V/0.0V F = 100 MHz
V
OUT
= 1.7V/0.7V
See
Figure 8
F
max
Maximum frequency
V
DD
= 3.3V
See
Figure 6
160
MHz
See
Figure 8
200
F
max(20)
Maximum frequency
V
DD
= 3.3 V
See
Figure 8
200
MHz
Maximum frequency
V
DD
= 2.5 V
Minimum pulse
V
DD
= 3.3 V
See
Figure 3
100
t
W
See
Figure 7
2
ns
Minimum pulse
V
DD
= 2.5 V
See
Figure 2
1
AC Switching Characteristics
@ 3.3V V
DD
= 3.3V ± 5%, T
A
=
–
40
°
C to +85
°
C (See
Figure 6
)
Parameter
Description
t
PLH
Propagation Delay
–
Low to High
t
PHL
Propagation Delay
–
High to Low
t
PHZ
Propagation Delay
–
High to High Z
t
PLZ
Propagation Delay
–
Low to High Z
t
R
Output Rise Time
t
F
Output Fall Time
t
SK(0)
Output Skew: Skew between outputs of the same package (in
phase)
t
SK(p)
Pulse Skew: Skew between opposite transitions of the same output
(t
PHL
–
t
PLH
)
t
SK(t)
Package Skew: Skew between outputs of different packages at the
same power supply voltage, temperature and package type.
t
OFF
Delay from OE to Driver Off
t
ON
Delay from OE to Driver on
Min.
1.5
1.5
Typ.
3
3
4
3
0.8
0.8
Max.
3.9
3.9
Unit
nS
nS
nS
nS
V/nS
V/nS
nS
See
Figure 9
See
Figure 10
See
Figure 9
See
Figure 12
0.2
See
Figure 11
0.2
nS
See
Figure 13
0.3
nS
4.0
4.0
nS
nS
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