- 您现在的位置：买卖IC网 > PDF目录380126 > CY2DL814 (Cypress Semiconductor Corp.) 1:4 Clock Fanout Buffer PDF资料下载
参数资料
| 型号： | CY2DL814 |
| 厂商： | Cypress Semiconductor Corp. |
| 英文描述： | 1:4 Clock Fanout Buffer |
| 中文描述： | 1:4时钟扇出缓冲器 |
| 文件页数： | 2/8页 |
| 文件大小： | 111K |
| 代理商： | CY2DL814 |
ComLink
Series
CY2DL814
Document #: 38-07057 Rev. *A
Page 2 of 8
Pin Description
Maximum Ratings
[1][2]
Storage Temperature: ................................
–
65
°
C to + 150
°
C
Ambient Temperature:...................................
–
40
°
C to +85
°
C
Supply Voltage to Ground Potential
(Inputs and V
CC
only).......................................
–
0.3V to 4.6V
Supply Voltage to Ground Potential
(Outputs only)........................................
–
0.3V to V
DD
+ 0.3V
DC Input Voltage ...................................
–
0.3V to V
DD
+ 0.3V
DC Output Voltage.................................
–
0.3V to V
DD
+ 0.9V
Power Dissipation........................................................0.75W
Note:
1.
Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
2.
Pin Number
6,7
Pin Name
IN+, IN
–
Pin Standard Interface
Configurable
Description
Differential input pair or single line.
LVPECL default. See config below.
Converts into a High drive driver from a standard LVDS.
Standard drive (logic = 0)
B/High drive/Bus (logic = 1)
Converts inputs (IN
+
/IN
–
), (EN, EN#) from the default
LVPECL/LVDS (logic = 0)
To LVTTL/LVCMOS (logic = 1)
Enable/disable logic. See
Table 1
below for details.
Differential outputs.
3
CNTRL
LVTTL/LVCMOS
2
CONFIG
LVTTL/LVCMOS
1,8
EN1, EN2
Q1A, Q1B, Q2A,
Q2B,
Q3A, Q3B, Q4A,
Q4B
V
DD
G
ND
LVTTL/LVCMOS
LDVS
16,15,14,13
12,11,10,9
4
5
POWER
POWER
Positive supply voltage
Ground
Table 1. EN1 EN2 Function Table
–
Differential Input Mode
Enable Logic
Input
Outputs
EN1
H
H
X
X
L
EN2
X
X
L
L
H
IN+
H
L
H
L
X
IN
–
L
H
L
H
X
QnA
H
L
H
L
Z
QnB
L
H
L
H
Z
Table 2. Output Drive Control for Standard and Bus/B/High Drive B
CNTRL Pin 3 Binary Value
0
Drive STD
Standard
Impedance
100 ohm
50 ohm
100 ohm
50 ohm
Output Voltage Value
V0 = Voutput
V = 1/2 * V0
V = 2 * V0
V = V0
1
High Drive/Bus/B
相关PDF资料 |
PDF描述 |
|---|---|
| CY2DL814SC | 1:4 Clock Fanout Buffer |
| CY2DL814SCT | 1:4 Clock Fanout Buffer |
| CY2DL814ZC | DB37 INTERFACE DATA CBL DB37 Male - DB37 Female |
| CY2DL814SI | 1:4 Clock Fanout Buffer |
| CY2DL814SIT | 1:4 Clock Fanout Buffer |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CY2DL814_05 | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:ComLink⑩ Series |
| CY2DL814SC | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:1:4 Clock Fanout Buffer |
| CY2DL814SCT | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:ComLink⑩ Series |
| CY2DL814SI | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:1:4 Clock Fanout Buffer |
| CY2DL814SIT | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:ComLink⑩ Series |
发布紧急采购，3分钟左右您将得到回复。