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参数资料
| 型号： | CY39200V388-200MGI |
| 厂商： | Cypress Semiconductor Corp. |
| 英文描述： | CPLDs at FPGA Densities |
| 中文描述： | CPLD器件在FPGA的密度 |
| 文件页数： | 20/86页 |
| 文件大小： | 1235K |
| 代理商： | CY39200V388-200MGI |
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Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *H
Page 20 of 86
t
MACCLMS2
Internal Parameters
t
CLMCLAA
Macrocell clock to cluster memory output clock in the same cluster
Asynchronous cluster memory access time from input of cluster memory to output of cluster memory
Channel Memory Timing Parameter Descriptions
Over the Operating Range
Parameter
Dual Port Asynchronous Mode Parameters
t
CHMAA
Channel memory access time. Delay from address change to Read data out
t
CHMPWE
Write enable pulse width
t
CHMSA
Address set-up to the beginning of Write enable with both signals from the same I/O block
t
CHMHA
Address hold after the end of Write enable with both signals from the same I/O block
t
CHMSD
Data set-up to the end of Write enable
t
CHMHD
Data hold after the end of Write enable
t
CHMBA
Channel memory asynchronous dual port address match (busy access time)
Dual Port Synchronous Mode Parameters
Clock cycle time for flow through Read and Write operations (from macrocell register through channel
memory back to a macrocell register in the same cluster)
Clock cycle time for pipelined Read and Write operations (from channel memory input register through the
memory to channel memory output register)
t
CHMS
Address, data, and WE set-up time of pin inputs, relative to a global clock
t
CHMH
Address, data, and WE hold time of pin inputs, relative to a global clock
t
CHMDV1
Global clock to data valid on output pins for flow through data
t
CHMDV2
Global clock to data valid on output pins for pipelined data.
t
CHMBDV
Channel memory synchronous dual-port address match (busy, clock to data valid)
t
CHMMACS1
Channel memory input clock to macrocell clock in the same cluster
t
CHMMACS2
Channel memory output clock to macrocell clock in the same cluster
t
MACCHMS1
Macrocell clock to channel memory input clock in the same cluster
t
MACCHMS2
Macrocell clock to channel memory output clock in the same cluster
Synchronous FIFO Data Parameters
t
CHMCLK
Read and Write minimum clock cycle time
t
CHMFS
Data, Read enable, and Write enable set-up time relative to pin inputs
t
CHMFH
Data, Read enable, and Write enable hold time relative to pin inputs
t
CHMFRDV
Data access time to output pins from rising edge of Read clock (Read clock to data valid)
t
CHMMACS
Channel memory FIFO Read clock to macrocell clock for Read data
t
MACCHMS
Macrocell clock to channel memory FIFO Write clock for Write data
Synchronous FIFO Flag Parameters
t
CHMFO
Read or Write clock to respective flag output at output pins
t
CHMMACF
Read or Write clock to macrocell clock with FIFO flag
t
CHMFRS
Master Reset Pulse Width
t
CHMFRSR
Master Reset Recovery Time
t
CHMFRSF
Master Reset to Flag and Data Output Time
t
CHMSKEW1
Read/Write Clock Skew Time for Full Flag
t
CHMSKEW2
Read/Write Clock Skew Time for Empty Flag
t
CHMSKEW3
Read/Write Clock Skew Time for Boundary Flags
Description
t
CHMCYC1
t
CHMCYC2
Cluster Memory Timing Parameter Descriptions
Over the Operating Range (continued)
Parameter
Description
相关PDF资料 |
PDF描述 |
|---|---|
| CY39200V388-200NC | CPLDs at FPGA Densities |
| CY39200V388-200NI | CPLDs at FPGA Densities |
| CY39200V388-200NTC | CPLDs at FPGA Densities |
| CY39200V388-200NTI | CPLDs at FPGA Densities |
| CY39200V388-233BBC | CPLDs at FPGA Densities |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CY39200V388-233MGC | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39200V388-233MGI | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39200V388-233NTC | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39200V388-83MGC | 制造商:Cypress Semiconductor 功能描述: |
| CY39200V484-125BBC | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
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