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| 型号： | CY39200V388-233BGC |
| 厂商： | Cypress Semiconductor Corp. |
| 英文描述： | CPLDs at FPGA Densities |
| 中文描述： | CPLD器件在FPGA的密度 |
| 文件页数： | 10/86页 |
| 文件大小： | 1235K |
| 代理商： | CY39200V388-233BGC |
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Delta39K ISR
CPLD Family
Document #: 38-03039 Rev. *H
Page 10 of 86
I/O Signals
There are four dedicated inputs (GCTL[3:0]) that are used as
Global I/O Control Signals available to every I/O cell. These
global I/O control signals may be used as output enables,
register resets and register clock enables as shown in
Figure 8
. These global control signals, driven from four
dedicated pins, can only be used as active-high signals and
are available only to the I/O cells thereby implementing fast
resets, register and output enables.
In addition, there are six OCC signals available to each I/O
cell. These control signals may be used as output enables,
register resets and register clock enables as shown in
Figure 8
. Unlike global control signals, these OCC signal can
be driven from internal logic or and I/O pin.
One of the four global clocks can be selected as the clock for
the I/O cell register. The clock mux output is an input to a clock
polarity mux that allows the input/output register to be clocked
on either edge of the clock
Slew Rate Control
The output buffer has a slew rate control option. This allows
the output buffer to slew at a fast rate (3 V/ns) or a slow rate
(1 V/ns). All I/Os default to fast slew rate. For designs
concerned with meeting FCC emissions standards the slow
edge provides for lower system noise. For designs requiring
very high performance the fast edge rate provides maximum
system performance.
D
Q
RES
E
G
O
G
Slew
Rate
Control
C
I/O
From
Output PIM
To Routing
Channel
OE Mux
Register Input
Mux
Register Enable
Mux
Output Mux
Clock Mux
Clock
Polarity
Mux
Register Reset
Mux
Input
Mux
Bus
Hold
C
D
Q
RES
C
Registered OE
Mux
C
C
C
3
C
3
C
2
3
C
C
C
Figure 8. Block Diagram of I/O Cell
Table 3.
I/O Standards
I/O
Standard
V
REF
(V)
Min.
N/A
V
CCIO
Termination
Voltage (V
TT
)
Max.
LVTTL
LVCMOS
LVCMOS3
LVCMOS2
LVCMOS18
3.3V PCI
GTL+
SSTL3 I
SSTL3 II
SSTL2 I
SSTL2 II
HSTL I
HSTL II
HSTL III
HSTL IV
3.3V
3.3V
3.0V
2.5V
1.8V
3.3V
N/A
3.3V
3.3V
2.5V
2.5V
1.5V
1.5V
1.5V
1.5V
N/A
N/A
N/A
N/A
N/A
N/A
1.5
1.5
1.5
1.25
1.25
0.75
0.75
1.5
1.5
0.9
1.3
1.3
1.15
1.15
0.68
0.68
0.68
0.68
1.1
1.7
1.7
1.35
1.35
0.9
0.9
0.9
0.9
相关PDF资料 |
PDF描述 |
|---|---|
| CY39200V388-233BGI | CPLDs at FPGA Densities |
| CY39200V388-233MBC | CPLDs at FPGA Densities |
| CY39200V388-233MBI | CPLDs at FPGA Densities |
| CY39200V388-233NC | CPLDs at FPGA Densities |
| CY39200V388-233NI | CPLDs at FPGA Densities |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CY39200V388-233MGC | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39200V388-233MGI | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39200V388-233NTC | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
| CY39200V388-83MGC | 制造商:Cypress Semiconductor 功能描述: |
| CY39200V484-125BBC | 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:CPLDs at FPGA Densities |
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