参数资料
型号: CY7C0851AV-133AXI
厂商: CYPRESS SEMICONDUCTOR CORP
元件分类: SRAM
英文描述: FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
中文描述: 64K X 36 DUAL-PORT SRAM, 4 ns, PQFP176
封装: 24 X 24 MM, 1.40 MM HEIGHT, LEAD FREE, TQFP-176
文件页数: 21/36页
文件大小: 956K
代理商: CY7C0851AV-133AXI
CY7C0850AV,CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document #: 38-06070 Rev. *J
Page 28 of 36
Figure 23. MailBox Interrupt Timing[57, 58, 59, 60, 61]
Table 7. Read/Write and Enable Operation (Any Port) [64, 65, 62, 63]
Inputs
Outputs
Operation
OE
CLK
CE0
CE1
R/W
DQ0 – DQ35
X
H
X
High-Z
Deselected
X
L
X
High-Z
Deselected
XL
H
L
DIN
Write
LL
H
DOUT
Read
H
X
L
H
X
High-Z
Outputs disabled
Switching Waveforms (continued)
tCH2
tCL2
tCYC2
CLKL
tCH2
tCL2
tCYC2
CLKR
3FFFF
tSA
tHA
An+3
An
An+1
An+2
L_PORT
ADDRESS
Am
Am+4
Am+1
3FFFF
Am+3
R_PORT
ADDRESS
INTR
tSA
tHA
tSINT
tRINT
Notes
57. CE0 = OE = ADS = CNTEN = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH.
58. Address “3FFFF” is the mailbox location for R_Port of a 9M device.
59. L_Port is configured for Write operation, and R_Port is configured for Read operation.
60. At least one byte enable (B0 – B3) is required to be active during interrupt operations.
61. Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock.
62. OE is an asynchronous input signal.
63. When CE changes state, deselection and Read happen after one cycle of latency.
64. 9 M device has 18 address bits, 4M device has 17 address bits, 2 M device has 16 address bits, and 1M device has 15 address bits.
65. “X” = “Don’t Care,” “H” = HIGH, “L” = LOW.
相关PDF资料
PDF描述
CY7C0851AV-133BBI FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0851AV-167BBXC FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0852AV-133AXC FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0852AV-133AXI FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0852AV-133BBI FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
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