参数资料
型号: CY7C0852AV-133AXC
厂商: CYPRESS SEMICONDUCTOR CORP
元件分类: SRAM
英文描述: FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
中文描述: 128K X 36 DUAL-PORT SRAM, 4 ns, PQFP176
封装: 24 X 24 MM, 1.40 MM HEIGHT, LEAD FREE, TQFP-176
文件页数: 11/36页
文件大小: 956K
代理商: CY7C0852AV-133AXC
CY7C0850AV,CY7C0851V/CY7C0851AV
CY7C0852V/CY7C0852AV
CY7C0853V/CY7C0853AV
Document #: 38-06070 Rev. *J
Page 19 of 36
Figure 10. Bank Select Read[31, 32]
Figure 11. Read-to-Write-to-Read (OE = LOW)[30, 33, 34, 35, 36]
Switching Waveforms (continued)
Q3
Q1
Q0
Q2
A0
A1
A2
A3
A4
A5
Q4
A0
A1
A2
A3
A4
A5
tSA
tHA
tSC
tHC
tSA
tHA
tSC
tHC
tSC
tHC
tSC tHC
tCKHZ
tDC
tCD2
tCKLZ
tCD2
tCKHZ
tCKLZ
tCD2
tCKHZ
tCKLZ
tCD2
tCH2
tCL2
tCYC2
CLK
ADDRESS(B1)
CE(B1)
DATAOUT(B2)
DATAOUT(B1)
ADDRESS(B2)
CE(B2)
tCYC2
tCL2
tCH2
tHC
tSC
tHW
tSW
tHA
tSA
tHW
tSW
tCD2
tCKHZ
tSD tHD
NO OPERATION
WRITE
READ
CLK
CE
R/W
ADDRESS
DATAIN
DATAOUT
An
An+1
An+2
Dn+2
An+3
An+4
Qn
Qn+3
Qn+1
tCD2
tCKLZ
Notes
31. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress CY7C0851V/CY7C0851AV/CY7C0852V/CY7C0852AV
device from this data sheet. ADDRESS(B1) = ADDRESS(B2).
32. ADS = CNTEN= B0 – B3 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH.
33. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
34. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
35. CE0 = OE = B0 – B3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.
36. CE0 = B0 – B3 = R/W = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be completed
(labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK.
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CY7C0852AV-133AXI FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
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