参数资料
型号: CY7C09099V-12AXC
厂商: CYPRESS SEMICONDUCTOR CORP
元件分类: SRAM
英文描述: 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM
中文描述: 128K X 8 DUAL-PORT SRAM, 25 ns, PQFP100
封装: ROHS COMPLIANT, PLASTIC, MS-026, TQFP-100
文件页数: 11/28页
文件大小: 657K
代理商: CY7C09099V-12AXC
CY7C09089V/99V
CY7C09179V/99V
Document #: 38-06043 Rev. *F
Page 19 of 28
Figure 13. Flow-through Read-to-Write-to-Read (OE Controlled)[46, 47, 48, 49, 50]
Switching Waveforms (continued)
Qn
tCH1
tCL1
tCYC1
tSC
tHC
tSW
tHW
tSA
tHA
tCD1
tDC
tOHZ
READ
An
An+1
An+2
An+3
An+4
An+5
Dn+2
Dn+3
tSW
tHW
tSD
tHD
tCD1
tCKLZ
tDC
Qn+4
tOE
WRITE
READ
CLK
CE0
CE1
ADDRESS
R/W
DATAIN
DATAOUT
OE
Notes
46. ADS = VIL, CNTEN and CNTRST = VIH.
47. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2; Each Bank consists of one Cypress dual-port device from this datasheet.
ADDRESS(B1) = ADDRESS(B2).
48. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
49. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
50. During “No Operation”, data in memory at the selected address may be corrupted and should be re-written to ensure data integrity.
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