参数资料
型号: CY7C09099V-12AXC
厂商: CYPRESS SEMICONDUCTOR CORP
元件分类: SRAM
英文描述: 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM
中文描述: 128K X 8 DUAL-PORT SRAM, 25 ns, PQFP100
封装: ROHS COMPLIANT, PLASTIC, MS-026, TQFP-100
文件页数: 4/28页
文件大小: 657K
代理商: CY7C09099V-12AXC
CY7C09089V/99V
CY7C09179V/99V
Document #: 38-06043 Rev. *F
Page 12 of 28
Port to Port Delays
tCWDD
Write Port Clock HIGH to Read Data Delay
30
35
40
40
ns
tCCS
Clock to Clock Set-Up Time
9
10
15
15
ns
Switching Waveforms
Figure 6. Read Cycle for Flow-through Output (FT/PIPE = VIL)[19, 20, 21, 22]
Switching Characteristics (continued)
Over the Operating Range
Parameter
Description
CY7C09079V/89V/99V
CY7C09179V/89V/99V
Unit
-6[16]
-7[16]
-9
-12
Min
Max
Min
Max
Min
Max
Min
Max
tCH1
tCL1
tCYC1
tSC
tHC
tDC
tOHZ
tOE
tSC
tHC
tSW
tHW
tSA
tHA
tCD1
tCKHZ
tDC
tOLZ
tCKLZ
An
An+1
An+2
An+3
Qn
Qn+1
Qn+2
CLK
CE0
CE1
R/W
ADDRESS
DATAOUT
OE
Notes
19. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
20. ADS = VIL, CNTEN and CNTRST = VIH.
21. The output is disabled (high-impedance state) by CE0 = VIH or CE1 = VIL following the next rising edge of the clock.
22. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
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CY7C09099V-7AXI 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM
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