参数资料
型号: CY7C09199V-9AXC
厂商: CYPRESS SEMICONDUCTOR CORP
元件分类: SRAM
英文描述: 3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM
中文描述: 128K X 9 DUAL-PORT SRAM, 20 ns, PQFP100
封装: ROHS COMPLIANT, PLASTIC, MS-026, TQFP-100
文件页数: 10/28页
文件大小: 657K
代理商: CY7C09199V-9AXC
CY7C09089V/99V
CY7C09179V/99V
Document #: 38-06043 Rev. *F
Page 18 of 28
Figure 12. Flow-through Read-to-Write-to-Read (OE = VIL)[41, 42, 43, 44, 45]
Switching Waveforms (continued)
tCH1
tCL1
tCYC1
tSC
tHC
tSW
tHW
tSA
tHA
tSW
tHW
tSD
tHD
An
An+1
An+2
An+3
An+4
Dn+2
Qn
Qn+1
Qn+3
tCD1
tDC
tCKHZ
tCD1
tCKLZ
tDC
READ
NO
OPERATION
WRITE
READ
CLK
CE0
CE1
ADDRESS
R/W
DATAIN
DATAOUT
Notes
41. ADS = VIL, CNTEN and CNTRST = VIH.
42. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
43. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
44. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
45. During “No Operation”, data in memory at the selected address may be corrupted and should be re-written to ensure data integrity.
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