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参数资料
| 型号： | CY7C1157V18 |
| 厂商： | Cypress Semiconductor Corp. |
| 英文描述： | 18-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) |
| 中文描述： | 18兆位的DDR - II SRAM的2字突发架构（2.0周期读写延迟） |
| 文件页数： | 3/27页 |
| 文件大小： | 969K |
| 代理商： | CY7C1157V18 |
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CY7C1146V18
CY7C1157V18
CY7C1148V18
CY7C1150V18
Document Number: 001-06621 Rev. *C
Page 11 of 27
The write cycle descriptions of CY7C1148V18 follows, [3, 9]
BWS0 BWS1 BWS2 BWS3
KK
Comments
LLLL
L – H
–
When the Data portion of a write sequence is active, all four bytes (D[35:0]) are
written into the device.
LLLL
–
L – H When the Data portion of a write sequence is active, all four bytes (D[35:0]) are
written into the device.
L
H
L – H
–
When the Data portion of a write sequence is active, only the lower byte (D[8:0]) is
written into the device. D[35:9] remains unaltered.
L
H
–
L – H When the Data portion of a write sequence is active, only the lower byte (D[8:0]) is
written into the device. D[35:9] remains unaltered.
H
L
H
L – H
–
When the Data portion of a write sequence is active, only the byte (D[17:9]) is written
into the device. D[8:0] and D[35:18] remains unaltered.
H
L
H
–
L – H When the Data portion of a write sequence is active, only the byte (D[17:9]) is written
into the device. D[8:0] and D[35:18] remains unaltered.
H
L
H
L – H
–
When the Data portion of a write sequence is active, only the byte (D[26:18]) is
written into the device. D[17:0] and D[35:27] remains unaltered.
H
L
H
–
L – H When the Data portion of a Write sequence is active, only the byte (D[26:18]) is
written into the device. D[17:0] and D[35:27] remains unaltered.
H
L
L – H
–
When the Data portion of a write sequence is active, only the byte (D[35:27]) is
written into the device. D[26:0] remains unaltered.
H
L
–
L – H When the Data portion of a write sequence is active, only the byte (D[35:27]) is
written into the device. D[26:0] remains unaltered.
HHHH
L – H
–
No data is written into the device when this portion of a write operation is active.
HHHH
–
L – H No data is written into the device when this portion of a write operation is active.
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| CY7C1163KV18-400BZI | 功能描述:静态随机存取存储器 18MB (1Mx18) 1.8v 400MHz DDR II 静态随机存取存储器 RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| CY7C1163KV18-450BZC | 功能描述:静态随机存取存储器 18MB (1Mx18) 1.8v 450MHz DDR II 静态随机存取存储器 RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
| CY7C1163KV18-550BZC | 功能描述:静态随机存取存储器 18MB (1Mx18) 1.8v 550MHz DDR II 静态随机存取存储器 RoHS:否 制造商:Cypress Semiconductor 存储容量:16 Mbit 组织:1 M x 16 访问时间:55 ns 电源电压-最大:3.6 V 电源电压-最小:2.2 V 最大工作电流:22 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:TSOP-48 封装:Tray |
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