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参数资料
型号： CY7C1481V25-100BZC
厂商： CYPRESS SEMICONDUCTOR CORP
元件分类： DRAM
英文描述： 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
中文描述： 2M X 36 CACHE SRAM, 8.5 ns, PBGA165
封装： 15 X 17 MM, 1.40 MM HEIGHT, FBGA-165
文件页数： 10/30页
文件大小： 1028K
代理商： CY7C1481V25-100BZC
CY7C1481V25
CY7C1483V25
CY7C1487V25
Document #: 38-05281 Rev. *H
Page 10 of 30
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
ZZ > V
DD
– 0.2V
ZZ > V
DD
– 0.2V
ZZ < 0.2V
Min.
Max.
Unit
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Sleep mode standby current
120
mA
Device operation to ZZ
2t
CYC
ns
ZZ recovery time
2t
CYC
ns
ZZ active to sleep current
This parameter is sampled
2t
CYC
ns
ZZ Inactive to exit sleep current
This parameter is sampled
0
ns
Truth Table
The truth table for CY7C1481V25, CY7C1483V25, and CY7C1487V25 follows.
[3, 4, 5, 6, 7]
Cycle Description
ADDRESS
Used
None
CE
1
CE
2
CE
3
ZZ
ADSP
ADSC
ADV WRITE
OE
CLK
DQ
Deselected Cycle,
Power Down
Deselected Cycle,
Power Down
Deselected Cycle,
Power Down
Deselected Cycle,
Power Down
Deselected Cycle,
Power Down
Sleep Mode, Power Down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
H
X
X
L
X
L
X
X
X
L-H
Tri-State
None
L
L
X
L
L
X
X
X
X
L-H
Tri-State
None
L
X
H
L
L
X
X
X
X
L-H
Tri-State
None
L
L
X
L
H
L
X
X
X
L-H
Tri-State
None
X
X
X
L
H
L
X
X
X
L-H
Tri-State
None
External
External
External
External
External
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
X
L
L
L
L
L
X
X
H
H
X
H
X
X
H
H
X
H
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
X
X
X
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
L
L
L
L
L
L
H
H
H
H
H
H
X
X
X
L
H
H
H
H
H
H
L
L
H
H
H
H
L
L
X
L
H
X
L
H
L
H
L
H
X
X
L
H
L
H
X
X
X
Tri-State
Q
Tri-State
D
Q
Tri-State
Q
Tri-State
Q
Tri-State
D
D
Q
Tri-State
Q
Tri-State
D
D
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
Notes
3. X=”Don't Care,” H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H.
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
. Writes may occur only on subsequent clocks after
the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to enable the outputs to tri-state. OE is a don't
care for the remainder of the write cycle.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
[+] Feedback
相关PDF资料
PDF描述
CY7C1481V25-100BZI 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
CY7C1481V25-100BZXC 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
CY7C1481V25-100BZXI 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
CY7C1481V25-133AXC 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
CY7C1481V25-133AXI 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
相关代理商/技术参数
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