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参数资料
| 型号： | CY7C343B-35JI |
| 厂商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 英文描述： | OT PLD, 35 ns, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 7/11页 |
| 文件大小： | 178K |
| 代理商： | CY7C343B-35JI |
CY7C343B
USE ULTRA37000TM FOR
ALL NEW DESIGNS
Document #: 38-03038 Rev. *B
Page 5 of 11
LOGIC ARRAY
CONTROL DELAY
tLAC
EXPANDER
DELAY
tEXP
CLOCK
DELAY
tIC
tRD
tCOMB
tLATCH
INPUT
DELAY
tIN
PIA
DELAY
tPIA
REGISTER
OUTPUT
DELAY
tOD
tXZ
tZX
LOGIC ARRAY
DELAY
tLAD
FEEDBACK
DELAY
tFD
I/O DELAY
tIO
INPUT/
OUTPUT
INPUT
SYSTEM CLOCK DELAY tICS
tRH
tRSU
tPRE
tCLR
Figure 1. CY7C343B Internal Timing Model
External Synchronous Switching Characteristics Over Operating Range
Parameter
Description
7C343B-25
7C343B-30
7C343B-35
Unit
Min.
Max.
Min.
Max.
Min.
Max.
tPD1
Dedicated Input to Combinatorial Output
Delay[4]
Com’l/Ind
25
30
35
ns
tPD2
I/O Input to Combinatorial Output Delay[4]
Com’l/Ind
40
45
55
ns
tSU
Global clock setup time
Com’l/ Ind
15
20
25
ns
tCO1
Synchronous Clock Input to Output Delay[3] Com’l/Ind
14
16
20
ns
tH
Input Hold Time from Synchronous Clock
Input
Com’l/Ind
0
ns
tWH
Synchronous Clock Input HIGH Time
Com’l/Ind
8
10
12.5
ns
tWL
Synchronous Clock Input LOW Time
Com’l/Ind
8
10
12.5
ns
fMAX
Maximum Register Toggle Frequency[5]
Com’l/Ind
62.5
50
40
MHz
tCNT
Minimum Global Clock Period
Com’l/Ind
20
25
30
ns
tODH
Output Data Hold Time After Clock
Com’l/Ind
2
ns
fCNT
Maximum Internal Global Clock
Frequency[6]
Com’l/Ind
50
40
33.3
MHz
Notes:
4. C1 = 35 pF.
5. The fMAX values represent the highest frequency for pipeline data.
6. This parameter is measured with a 16-bit counter programmed into each LAB.
相关PDF资料 |
PDF描述 |
|---|---|
| CY7C343B-25HC | UV PLD, 25 ns, CQCC44 |
| CY7C343B-25HI | UV PLD, 25 ns, CQCC44 |
| CY7C343B-35HC | UV PLD, 35 ns, CQCC44 |
| CY7C343B-35HI | UV PLD, 35 ns, CQCC44 |
| CY7C344B-25JCT | OT PLD, 25 ns, PQCC28 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| CY7C344-15JC | 制造商:Cypress Semiconductor 功能描述: |
| CY7C344-15PC | 制造商:Cypress Semiconductor 功能描述:CPLD MAX? Family 600 Gates 32 Macro Cells 0.8um Technology 5V 28-Pin PDIP |
| CY7C344-20JC | 制造商:Cypress Semiconductor 功能描述:CPLD MAX? Family 600 Gates 32 Macro Cells 0.8um Technology 5V 28-Pin PLCC |
| CY7C344-20JI | 制造商:Cypress Semiconductor 功能描述:CPLD MAX? Family 600 Gates 32 Macro Cells 0.8um (CMOS) Technology 5V 28-Pin PLCC 制造商:Cypress Semiconductor 功能描述:Simple EPLD, Programmable Array Logic, 28 Pin, Plastic, PLCC |
| CY7C34420WC | 制造商:CYPRESS 功能描述:* |
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