参数资料
| 型号： | CYW150OXC |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 4/14页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK 440BX AGP 56SSOP |
| 标准包装： | 26 |
| 类型： | 时钟/频率合成器，扩展频谱时钟发生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服务器 |
| 输入： | 时钟，晶体 |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:33 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 150MHz |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 56-BSSOP（0.295"，7.50mm 宽） |
| 供应商设备封装： | 56-SSOP |
| 包装： | 管件 |
CYW150
...................... Document #: 38-07177 Rev. *B Page 12 of 14
Layout Example
tD
Duty Cycle
Measured on rising and falling edge at
1.5V
45
55
45
55
%
tSK
Output Skew
Measured on rising and falling edge at
1.5V
250
ps
tPD
Propagation Delay
Measured from SDRAMIN
3.7
ns
Zo
AC Output Impedance
Average value during switching
transition. Used for determining series
termination value.
15
48-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
CPU = 66.8/100 MHz
Unit
Min.
Typ.
Max.
f
Frequency, Actual
Determined by PLL divider ratio (see m/n below)
48.008
MHz
fD
Deviation from 48 MHz
(48.008 – 48)/48
+167
ppm
m/n
PLL Ratio
(14.31818 MHz x 57/17 = 48.008 MHz)
57/17
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
0.5
2
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
0.5
2
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
45
55
%
fST
Frequency Stabilization
from Power-up (cold
start)
Assumes full supply voltage reached within 1 ms from
power-up. Short cycles exist prior to frequency stabili-
zation.
3ms
Zo
AC Output Impedance
Average value during switching transition. Used for deter-
mining series termination value.
25
24-MHz Clock Output (Lump Capacitance Test Load = 20 pF
Parameter
Description
Test Condition/Comments
CPU = 66.8/100 MHz
Unit
Min.
Typ.
Max.
f
Frequency, Actual
Determined by PLL divider ratio (see m/n below)
24.004
MHz
fD
Deviation from 24 MHz (24.004 – 24)/24
+167
ppm
m/n
PLL Ratio
(14.31818 MHz x 57/34 = 24.004 MHz)
57/34
tR
Output Rise Edge Rate Measured from 0.4V to 2.4V
0.5
2
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
0.5
2
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
45
55
%
fST
Frequency Stabilization
from Power-up (cold
start)
Assumes full supply voltage reached within 1 ms from
power-up. Short cycles exist prior to frequency stabili-
zation.
3ms
Zo
AC Output Impedance
Average value during switching transition. Used for
determining series termination value.
25
SDRAM 0:15, _F Clock Outputs (Lump Capacitance Test Load = 30 pF) (continued)
Parameter
Description
Test Condition/Comments
CPU = 66.8 MHz
CPU = 100 MHz
Unit
Min.
Typ.
Max.
Min.
Typ.
Max.
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