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参数资料
| 型号： | DAC1008D650HN |
| 厂商： | NXP Semiconductors N.V. |
| 元件分类： | 外设及接口 |
| 英文描述： | Dual 10-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating |
| 封装： | DAC1008D650HN/C1<SOT804-3|<<<1<Always Pb-free,;DAC1008D650HN/C1<SOT804-3|<<<1<Always Pb-free,; |
| 文件页数： | 15/98页 |
| 文件大小： | 551K |
| 代理商： | DAC1008D650HN |
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DAC1008D650
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 17 December 2010
15 of 98
NXP Semiconductors
DAC1008D650
2
×
, 4
×
or 8
×
interpolating DAC with JESD204A
10.2.4
Descrambler
The descrambler is a 16-bit parallel self-synchronous descrambler based on the
polynomial 1 + x
14
+ x
15
. This processing can be turned off.
10.2.5
Inter-lane alignment
This feature removes strict PCB design skew compensation between the lanes.
10.2.5.1
Single device operation
This module handles the alignment of the four data streams. Because of inter-lane skew
and each PLL per lane concept, these alignment characters may be received at different
times by the receivers. After the synchronization period, the lock signal will be HIGH. This
enables the receipt of K28.3 /A/ characters.
The ILA_CNTRL register’s SEL_ILA[1:0] bits select which K28.3 /A/ symbol triggers the
initial lane alignment:“00” = 1st /A/ symbol, “01” = 2nd /A/ symbol, “10” = 3rd /A/ symbol,
“11” = 4th /A/ symbol;
Table 86 on page 61
. When all receivers have received their first
selected /A/, they start propagating the received data to the frame assembly module at the
same point in time.
This module can compensate for up to
±
7 frame clock period misalignments between the
lanes.
When initial lane alignment is not supported, the manual alignment mode can be used.
After the initial ILA sequence, the lane alignment monitoring starts. If the received user
data contains a K28.3 /A/ symbol:
its position is compared to the value of the alignment monitor counter
if two successive K28.3 /A/ symbols have been received at a wrong position, a
realignment takes place
if the buffers are empty or overflow, this is indicated by the registers
ILA_BUF_ERR_LN0 to ILA_BUF_ERR_LN3
10.2.5.2
Multi-device operation
DAC1008D650 implements a multi-device inter-lane alignment that guarantees a skew of
less than one output period between them.
Two modes are available: master/slave and all slave. Both make use of the MDS_P and
MDS_N pins.
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| DAC1008D750HN | Dual 10-bit DAC; up to 750 Msps; 2×, 4× or 8× interpolating |
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| DAC1208D650HN | Dual 12-bit DAC; up to 650 Msps; 2×, 4× or 8× interpolating |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DAC1008D650HN/C1,5 | 功能描述:数模转换器- DAC DL 10BIT DAC 650MSPS 2X 4X OR 8X INT RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
| DAC1008D650HN-C1 | 功能描述:数模转换器- DAC RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
| DAC1008D750 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Dual 10-bit DAC up to 750 Msps 2×, 4× or 8× interpolating with JESD204A interface |
| DAC1008D750_11 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:Dual 10-bit DAC; up to 750 Msps; 2×, 4× or 8× interpolating |
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